dedicated output for LUT in GENERIC_SLICE
diff --git a/generic/cells.cc b/generic/cells.cc index 53886e3..3b75440 100644 --- a/generic/cells.cc +++ b/generic/cells.cc
@@ -44,13 +44,13 @@ if (type == ctx->id("GENERIC_SLICE")) { new_cell->params[ctx->id("K")] = std::to_string(ctx->args.K); new_cell->params[ctx->id("INIT")] = 0; - new_cell->params[ctx->id("FF_USED")] = 0; for (int i = 0; i < ctx->args.K; i++) add_port(ctx, new_cell.get(), "I[" + std::to_string(i) + "]", PORT_IN); add_port(ctx, new_cell.get(), "CLK", PORT_IN); + add_port(ctx, new_cell.get(), "F", PORT_OUT); add_port(ctx, new_cell.get(), "Q", PORT_OUT); } else if (type == ctx->id("GENERIC_IOB")) { new_cell->params[ctx->id("INPUT_USED")] = 0; @@ -80,18 +80,16 @@ } if (no_dff) { - replace_port(lut, ctx->id("Q"), lc, ctx->id("Q")); - lc->params[ctx->id("FF_USED")] = 0; + replace_port(lut, ctx->id("Q"), lc, ctx->id("F")); } } void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut) { - lc->params[ctx->id("FF_USED")] = 1; replace_port(dff, ctx->id("CLK"), lc, ctx->id("CLK")); if (pass_thru_lut) { - lc->params[ctx->id("INIT")] = 2; + lc->params[ctx->id("INIT")] = 0xAAAA; replace_port(dff, ctx->id("D"), lc, ctx->id("I[0]")); }
diff --git a/generic/examples/bitstream.py b/generic/examples/bitstream.py index 1ab94f0..6cd63a5 100644 --- a/generic/examples/bitstream.py +++ b/generic/examples/bitstream.py
@@ -6,7 +6,6 @@ param_map = { ("GENERIC_SLICE", "K"): ParameterConfig(write=False), ("GENERIC_SLICE", "INIT"): ParameterConfig(write=True, numeric=True, width=2**K), - ("GENERIC_SLICE", "FF_USED"): ParameterConfig(write=True, numeric=True, width=1), ("GENERIC_IOB", "INPUT_USED"): ParameterConfig(write=True, numeric=True, width=1), ("GENERIC_IOB", "OUTPUT_USED"): ParameterConfig(write=True, numeric=True, width=1), @@ -14,4 +13,4 @@ } with open("blinky.fasm", "w") as f: - write_fasm(ctx, param_map, f) \ No newline at end of file + write_fasm(ctx, param_map, f)
diff --git a/generic/examples/simple.py b/generic/examples/simple.py index 9339b68..9379b50 100644 --- a/generic/examples/simple.py +++ b/generic/examples/simple.py
@@ -9,6 +9,7 @@ for z in range(N): ctx.addWire(name="X%dY%dZ%d_CLK" % (x, y, z), type="BEL_CLK", x=x, y=y) ctx.addWire(name="X%dY%dZ%d_Q" % (x, y, z), type="BEL_Q", x=x, y=y) + ctx.addWire(name="X%dY%dZ%d_F" % (x, y, z), type="BEL_F", x=x, y=y) for i in range(K): ctx.addWire(name="X%dY%dZ%d_I%d" % (x, y, z, i), type="BEL_I", x=x, y=y) # Local wires @@ -29,6 +30,7 @@ ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="CLK", wire="X%dY%dZ%d_CLK" % (x, y, z)) for k in range(K): ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="I[%d]" % k, wire="X%dY%dZ%d_I%d" % (x, y, z, k)) + ctx.addBelOutput(bel="X%dY%d_SLICE%d" % (x, y, z), name="F", wire="X%dY%dZ%d_F" % (x, y, z)) ctx.addBelOutput(bel="X%dY%d_SLICE%d" % (x, y, z), name="Q", wire="X%dY%dZ%d_Q" % (x, y, z)) for x in range(X): @@ -48,6 +50,9 @@ # Pips from bel outputs to locals def create_output_pips(dst, offset, skip): for i in range(offset % skip, N, skip): + src = "X%dY%dZ%d_F" % (x, y, i) + ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_OUTPUT", + srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0)) src = "X%dY%dZ%d_Q" % (x, y, i) ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_OUTPUT", srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0)) @@ -69,4 +74,4 @@ create_neighbour_pips(dst, x, y+1, (l + 4) % Sl, Sl) create_neighbour_pips(dst, x+1, y-1, (l + 5) % Sl, Sl) create_neighbour_pips(dst, x+1, y, (l + 6) % Sl, Sl) - create_neighbour_pips(dst, x+1, y+1, (l + 7) % Sl, Sl) \ No newline at end of file + create_neighbour_pips(dst, x+1, y+1, (l + 7) % Sl, Sl)
diff --git a/generic/examples/simple.sh b/generic/examples/simple.sh index 8ae903f..76bc616 100755 --- a/generic/examples/simple.sh +++ b/generic/examples/simple.sh
@@ -1,4 +1,5 @@ #!/usr/bin/env bash set -ex yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v -${NEXTPNR:-../../nextpnr-generic} --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py +${NEXTPNR:-../../nextpnr-generic} --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py --write pnrblinky.json +yosys -p "read_verilog -lib ../synth/prims.v; read_json pnrblinky.json; dump -o blinky.il; show -format png -prefix blinky"
diff --git a/generic/examples/simple_timing.py b/generic/examples/simple_timing.py index 2ccb197..1067b55 100644 --- a/generic/examples/simple_timing.py +++ b/generic/examples/simple_timing.py
@@ -1,15 +1,13 @@ for cname, cell in ctx.cells: - if cell.type != "GENERIC_SLICE": - continue - if cname in ("$PACKER_GND", "$PACKER_VCC"): - continue - K = int(cell.params["K"]) - if int(cell.params["FF_USED"], 2) == 1: - ctx.addCellTimingClock(cell=cname, port="CLK") - for i in range(K): - ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK", - setup=ctx.getDelayFromNS(0.2), hold=ctx.getDelayFromNS(0)) - ctx.addCellTimingClockToOut(cell=cname, port="Q", clock="CLK", clktoq=ctx.getDelayFromNS(0.2)) - else: - for i in range(K): - ctx.addCellTimingDelay(cell=cname, fromPort="I[%d]" % i, toPort="Q", delay=ctx.getDelayFromNS(0.2)) \ No newline at end of file + if cell.type != "GENERIC_SLICE": + continue + if cname in ("$PACKER_GND", "$PACKER_VCC"): + continue + K = int(cell.params["K"]) + ctx.addCellTimingClock(cell=cname, port="CLK") + for i in range(K): + ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK", + setup=ctx.getDelayFromNS(0.2), hold=ctx.getDelayFromNS(0)) + ctx.addCellTimingClockToOut(cell=cname, port="Q", clock="CLK", clktoq=ctx.getDelayFromNS(0.2)) + for i in range(K): + ctx.addCellTimingDelay(cell=cname, fromPort="I[%d]" % i, toPort="F", delay=ctx.getDelayFromNS(0.2))
diff --git a/generic/synth/prims.v b/generic/synth/prims.v index 95fcfac..47a5df0 100644 --- a/generic/synth/prims.v +++ b/generic/synth/prims.v
@@ -21,21 +21,19 @@ module GENERIC_SLICE #( parameter K = 4, parameter [2**K-1:0] INIT = 0, - parameter FF_USED = 1'b0 ) ( input CLK, input [K-1:0] I, + output F, output Q ); + wire f_wire; - wire lut_q; - LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(lut_q)); + LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire)); - generate if (FF_USED) - DFF dff_i(.CLK(CLK), .D(lut_q), .Q(Q)); - else - assign Q = lut_q; - endgenerate + DFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q)); + + assign F = f_wire; endmodule module GENERIC_IOB #( @@ -56,4 +54,4 @@ generate if (INPUT_USED) assign O = PAD; endgenerate -endmodule \ No newline at end of file +endmodule