blob: b7cb1b86fa7d0f1d3b56701c7d231c3f31a519a2 [file] [log] [blame] [edit]
module top(input clk, output reg [7:0] leds);
reg [25:0] ctr;
always @(posedge clk)
ctr <= ctr + 1'b1;
assign leds = ctr[25:18];
endmodule