Merge origin/master into fix/2539 Resolve formatter_test.cc conflict by keeping both the #2539 line-continuation port-list regression and the #2542 continuation- comment tests from master.
diff --git a/verible/common/formatting/align.cc b/verible/common/formatting/align.cc index 74bc432..9f77014 100644 --- a/verible/common/formatting/align.cc +++ b/verible/common/formatting/align.cc
@@ -1001,6 +1001,20 @@ auto &line = node.Value(); auto ftokens = line.TokensRange(); + // Leading non-tree tokens before a forced wrap must stay on their own + // line. Putting them in a kInline prolog cell would glue e.g. `//\` onto + // the following `input` (GitHub issue 2539). Preserve original spacing + // for the whole row instead. Master's scanner already omits those + // leading tokens from column bids; this keeps ApplyAlignment from + // still inlining them. + if (align_actions.front().ftoken != ftokens.begin() && + align_actions.front().ftoken->before.break_decision == + SpacingOptions::kMustWrap) { + FormatUsingOriginalSpacing(TokenPartitionRange(*row, std::next(*row))); + ++row; + continue; + } + line.SetPartitionPolicy(PartitionPolicyEnum::kAlreadyFormatted); verible::TokenPartitionTree *current_cell = nullptr;
diff --git a/verible/verilog/formatting/align.cc b/verible/verilog/formatting/align.cc index 6640adb..24696c7 100644 --- a/verible/verilog/formatting/align.cc +++ b/verible/verilog/formatting/align.cc
@@ -147,6 +147,32 @@ b == AlignmentGroupBoundary::kBlankLinesAndSeparatorComments; } +// True when non-tree tokens (e.g. // comments, line-continuation `\`) precede +// the origin, and the first origin token must start a new line. Aligning such +// partitions would glue the leading tokens onto the origin line via kInline +// cells (GitHub issue 2539). Leave them out of alignment instead. +static bool PartitionHasLeadingTokensBeforeForcedWrap( + const TokenPartitionTree &partition) { + const auto &uwline = partition.Value(); + const verible::Symbol *origin = uwline.Origin(); + if (origin == nullptr) return false; + + const auto ftokens = uwline.TokensRange(); + if (ftokens.empty()) return false; + + const verible::SyntaxTreeLeaf *first_leaf = verible::GetLeftmostLeaf(*origin); + if (first_leaf == nullptr) return false; + + const verible::TokenInfo &first_tree_token = first_leaf->get(); + auto ftoken_it = ftokens.begin(); + while (ftoken_it != ftokens.end() && + *(ftoken_it->token) != first_tree_token) { + ++ftoken_it; + } + if (ftoken_it == ftokens.begin() || ftoken_it == ftokens.end()) return false; + return ftoken_it->before.break_decision == verible::SpacingOptions::kMustWrap; +} + static bool IgnoreCommentsAndPreprocessingDirectives( const TokenPartitionTree &partition) { const auto &uwline = partition.Value(); @@ -159,6 +185,8 @@ // ignore lines containing only comments if (TokensAreAllCommentsOrAttributes(token_range)) return true; + if (PartitionHasLeadingTokensBeforeForcedWrap(partition)) return true; + // ignore partitions belonging to preprocessing directives return IsPreprocessorKeyword( verilog_tokentype(token_range.front().TokenEnum())); @@ -199,6 +227,8 @@ return true; } + if (PartitionHasLeadingTokensBeforeForcedWrap(partition)) return true; + // ignore nested structs/unions if (verible::FindFirstSubtree( partition.Value().Origin(), [](const Symbol &symbol) {
diff --git a/verible/verilog/formatting/formatter_test.cc b/verible/verilog/formatting/formatter_test.cc index 5205a01..6cffcfe 100644 --- a/verible/verilog/formatting/formatter_test.cc +++ b/verible/verilog/formatting/formatter_test.cc
@@ -19380,6 +19380,32 @@ } } +// Regression for https://github.com/chipsalliance/verible/issues/2539: +// A // comment followed by a line-continuation `\` before aligned ports must +// not abort in align.h, and must keep the comment on its own line. +TEST(FormatterEndToEndTest, PortListCommentWithLineContinuationDoesNotAbort) { + static constexpr std::string_view kInput = + "module m (\n" + "//\\\n" + "input a\n" + ",input b\n" + ");\n" + "endmodule\n"; + FormatStyle style; + std::ostringstream stream; + const auto status = FormatVerilog(kInput, "<filename>", style, stream); + EXPECT_OK(status) << status.message(); + const std::string out = stream.str(); + // Must not glue the line-continuation onto the following port declaration. + EXPECT_THAT(out, testing::Not(testing::HasSubstr("//\\ input"))); + EXPECT_THAT(out, testing::HasSubstr("//\\")); + EXPECT_THAT(out, testing::HasSubstr("input a")); + EXPECT_THAT(out, testing::HasSubstr("input b")); + EXPECT_THAT(out, testing::HasSubstr("endmodule")); + // Comment line and first port remain on separate lines. + EXPECT_THAT(out, testing::ContainsRegex(R"(//\\\n\s*input a)")); +} + // Regression for https://github.com/chipsalliance/verible/issues/2542: // Continuation EOL comments after a wrapped assign must keep a stable column // across re-format (convergence).