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verible
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0ad00f0b2a11ef48b7dba9a85905e4f4e7a91c88
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.
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verilog
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tools
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lint
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testdata
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always_comb_blocking.sv
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module
always_comb_blocking
;
always_comb
a
<=
b
;
// [Style: combinational-logic] [always-comb-blocking]
endmodule
