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verible
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0ad00f0b2a11ef48b7dba9a85905e4f4e7a91c88
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.
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verilog
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tools
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lint
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testdata
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case_missing_default.sv
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// This case statement is missing a default case
function
automatic
int
foo
(
input bit
in
);
case
(
in
)
1
:
return
0
;
endcase
endfunction
