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foss-fpga-tools
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third_party
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verible
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0ad00f0b2a11ef48b7dba9a85905e4f4e7a91c88
/
.
/
verilog
/
tools
/
lint
/
testdata
/
generate-label-module-body.sv
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// verilog_syntax: parse-as-module-body
// verilog_lint: waive legacy-generate-region
generate
if
(
foo
)
begin
baz bam
;
end
endgenerate
