Merge pull request #1574 from antmicro/msrs/fix-classpropertycolumnschemascanner Add more variants to ClassPropertyColumnSchemaScanner

diff --git a/.github/bin/smoke-test.sh b/.github/bin/smoke-test.sh
index c4f0f8a..4377a01 100755
--- a/.github/bin/smoke-test.sh
+++ b/.github/bin/smoke-test.sh

@@ -134,8 +134,8 @@
 ExpectedFailCount[lint:ibex]=14
 ExpectedFailCount[project:ibex]=192
 
-ExpectedFailCount[syntax:opentitan]=36
-ExpectedFailCount[lint:opentitan]=36
+ExpectedFailCount[syntax:opentitan]=35
+ExpectedFailCount[lint:opentitan]=35
 ExpectedFailCount[project:opentitan]=727
 
 ExpectedFailCount[syntax:Cores-VeeR-EH2]=2
@@ -169,7 +169,7 @@
 ExpectedFailCount[formatter:ivtest]=2
 ExpectedFailCount[project:ivtest]=217
 
-ExpectedFailCount[project:ZAP]=30
+ExpectedFailCount[project:ZAP]=29
 
 ExpectedFailCount[syntax:nontrivial-mips]=2
 ExpectedFailCount[lint:nontrivial-mips]=2
@@ -186,9 +186,9 @@
 ExpectedFailCount[formatter:scr1]=2
 ExpectedFailCount[project:scr1]=45
 
-ExpectedFailCount[syntax:basejump_stl]=461
-ExpectedFailCount[lint:basejump_stl]=461
-ExpectedFailCount[project:basejump_stl]=567
+ExpectedFailCount[syntax:basejump_stl]=462
+ExpectedFailCount[lint:basejump_stl]=462
+ExpectedFailCount[project:basejump_stl]=569
 
 # Ideally, we expect all tools to process all files with a zero exit code.
 # However, that is not always the case, so we document the current

diff --git a/README.md b/README.md
index 0f0cb5b..7c08a24 100644
--- a/README.md
+++ b/README.md

@@ -3,7 +3,7 @@
 
 
 [![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0)
-[![Continuous Integration](https://github.com/chipsalliance/verible/workflows/verible-ci/badge.svg)](https://github.com/chipsalliance/verible/actions/workflows/verible-ci.yml)
+[![Continuous Integration](https://github.com/chipsalliance/verible/workflows/ci/badge.svg)](https://github.com/chipsalliance/verible/actions/workflows/verible-ci.yml)
 [![codecov](https://codecov.io/gh/chipsalliance/verible/branch/master/graph/badge.svg?token=5f656dpmDT)](https://codecov.io/gh/chipsalliance/verible)
 
 <!--*

diff --git a/verilog/formatting/formatter_test.cc b/verilog/formatting/formatter_test.cc
index 5bebebd..ebf4358 100644
--- a/verilog/formatting/formatter_test.cc
+++ b/verilog/formatting/formatter_test.cc

@@ -3411,6 +3411,20 @@
         "  );\n"
         "endmodule\n",
     },
+    {// Two consecutive EOL comments in kDPIImportItem
+     "import \"DPI-C\" context function void foo(\n"
+     "  input bit first,\n"
+     "  // c3\n"
+     "  // c3+\n"
+     "  input bit second\n"
+     ");\n",
+     "import \"DPI-C\" context\n"
+     "    function void foo(\n"
+     "  input bit first,\n"
+     "  // c3\n"
+     "  // c3+\n"
+     "  input bit second\n"
+     ");\n"},
     {"import \"DPI-C\" context function void func(input bit impl_i,"
      "input bit op_i,"
      "input bit [5:0] mode_i,"
@@ -8084,6 +8098,19 @@
      "  generic_type_name_t third  // c\n"
      ";\n"
      "} type_t;\n"},
+    {"struct {logic test1; // c\n"
+     "logic test2;} test3;\n",
+     "struct {\n"
+     "  logic test1;  // c\n"
+     "  logic test2;\n"
+     "} test3;\n"},
+    {"struct {\n"
+     "  /* t */ logic test1; /* t */\n"
+     "/* t */ logic test2; }test3;\n",
+     "struct {\n"
+     "  /* t */ logic test1;  /* t */\n"
+     "  /* t */ logic test2;\n"
+     "} test3;\n"},
     // Continuation comment alignment
     {"`define BAR 1 // A\n"
      "module foo(); // B\n"