Sign in
foss-fpga-tools
/
third_party
/
verible
/
14ca40e153266700cfc79d0c1c3b2bfe8a6a77cc
/
.
/
verilog
/
tools
/
lint
/
testdata
/
generate_label_module.sv
blob: c3252073413e130844ee02a726c9a2876cf447b7 [
file
]
module
generate_label_module
;
// verilog_lint: waive legacy-generate-region
generate
if
(
foo
)
begin
baz bam
;
end
endgenerate
endmodule
