Fix `input real` and similar module declarations

Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>

verible/verilog/formatting/formatter_test.cc

diff --git a/verible/verilog/formatting/formatter_test.cc b/verible/verilog/formatting/formatter_test.cc
index fd82c72..7b1e66a 100644
--- a/verible/verilog/formatting/formatter_test.cc
+++ b/verible/verilog/formatting/formatter_test.cc
@@ -1509,6 +1509,119 @@
      "          int   b\n"   // direction missing
      ");\n"
      "endmodule\n"},
+    {"module t;\n"
+     "    input bit i_bit;\n"
+     "input   byte  i_byte ;\n"
+     "input chandle i_chandle;\n"
+     "input event i_event;\n"
+     "input int i_int;\n"
+     "input integer i_inte;\n"
+     "input longint i_longint;\n"
+     "input real i_real;\n"
+     "input realtime i_realtime;\n"
+     "input shortint i_shortint;\n"
+     "input shortreal i_shortreal;\n"
+     "input string i_string;\n"
+     "input time i_time;\n"
+     "     output bit o_bit;\n"
+     "output    byte   o_byte  ;  \n"
+     "output chandle o_chandle;\n"
+     "output event o_event;\n"
+     "output int o_int;\n"
+     "output integer o_inte;\n"
+     "output longint o_longint;\n"
+     "output real o_real;\n"
+     "output realtime o_realtime;\n"
+     "output shortint o_shortint;\n"
+     "output shortreal o_shortreal;\n"
+     "output string o_string;\n"
+     "output time o_time;\n"
+     "endmodule\n",
+     "module t;\n"
+     "  input bit i_bit;\n"
+     "  input byte i_byte;\n"
+     "  input chandle i_chandle;\n"
+     "  input event i_event;\n"
+     "  input int i_int;\n"
+     "  input integer i_inte;\n"
+     "  input longint i_longint;\n"
+     "  input real i_real;\n"
+     "  input realtime i_realtime;\n"
+     "  input shortint i_shortint;\n"
+     "  input shortreal i_shortreal;\n"
+     "  input string i_string;\n"
+     "  input time i_time;\n"
+     "  output bit o_bit;\n"
+     "  output byte o_byte;\n"
+     "  output chandle o_chandle;\n"
+     "  output event o_event;\n"
+     "  output int o_int;\n"
+     "  output integer o_inte;\n"
+     "  output longint o_longint;\n"
+     "  output real o_real;\n"
+     "  output realtime o_realtime;\n"
+     "  output shortint o_shortint;\n"
+     "  output shortreal o_shortreal;\n"
+     "  output string o_string;\n"
+     "  output time o_time;\n"
+     "endmodule\n"},
+    {"module t (\n"
+     "    input bit i_bit,\n"
+     "input     byte   i_byte  ,\n"
+     "input chandle i_chandle,\n"
+     "input event i_event,\n"
+     "input int i_int,\n"
+     "input integer i_inte,\n"
+     "input longint i_longint,\n"
+     "input real i_real,\n"
+     "input realtime i_realtime,\n"
+     "input shortint i_shortint,\n"
+     "input shortreal i_shortreal,\n"
+     "input string i_string,\n"
+     "input time i_time,\n"
+     "    output bit o_bit,\n"
+     "output     byte   o_byte  ,  \n"
+     "output chandle o_chandle,\n"
+     "output event o_event,\n"
+     "output int o_int,\n"
+     "output integer o_inte,\n"
+     "output longint o_longint,\n"
+     "output real o_real,\n"
+     "output realtime o_realtime,\n"
+     "output shortint o_shortint,\n"
+     "output shortreal o_shortreal,\n"
+     "output string o_string,\n"
+     "output time o_time);\n"
+     "endmodule\n",
+     "module t (\n"
+     "    input  bit       i_bit,\n"
+     "    input  byte      i_byte,\n"
+     "    input  chandle   i_chandle,\n"
+     "    input  event     i_event,\n"
+     "    input  int       i_int,\n"
+     "    input  integer   i_inte,\n"
+     "    input  longint   i_longint,\n"
+     "    input  real      i_real,\n"
+     "    input  realtime  i_realtime,\n"
+     "    input  shortint  i_shortint,\n"
+     "    input  shortreal i_shortreal,\n"
+     "    input  string    i_string,\n"
+     "    input  time      i_time,\n"
+     "    output bit       o_bit,\n"
+     "    output byte      o_byte,\n"
+     "    output chandle   o_chandle,\n"
+     "    output event     o_event,\n"
+     "    output int       o_int,\n"
+     "    output integer   o_inte,\n"
+     "    output longint   o_longint,\n"
+     "    output real      o_real,\n"
+     "    output realtime  o_realtime,\n"
+     "    output shortint  o_shortint,\n"
+     "    output shortreal o_shortreal,\n"
+     "    output string    o_string,\n"
+     "    output time      o_time\n"
+     ");\n"
+     "endmodule\n"},
     {"module m;foo bar(.baz({larry, moe, curly}));endmodule",
      "module m;\n"
      "  foo bar (.baz({larry, moe, curly}));\n"

verible/verilog/parser/verilog-parser_test.cc

diff --git a/verible/verilog/parser/verilog-parser_test.cc b/verible/verilog/parser/verilog-parser_test.cc
index 0600bb7..754498b 100644
--- a/verible/verilog/parser/verilog-parser_test.cc
+++ b/verible/verilog/parser/verilog-parser_test.cc
@@ -1390,6 +1390,62 @@
     "input logic [N:0] a;\n"
     "output logic co;\n"
     "endmodule",
+    "module t;\n"
+    "input bit i_bit;\n"
+    "input byte i_byte;\n"
+    "input chandle i_chandle;\n"
+    "input event i_event;\n"
+    "input int i_int;\n"
+    "input integer i_inte;\n"
+    "input longint i_longint;\n"
+    "input real i_real;\n"
+    "input realtime i_realtime;\n"
+    "input shortint i_shortint;\n"
+    "input shortreal i_shortreal;\n"
+    "input string i_string;\n"
+    "input time i_time;\n"
+    "output bit o_bit;\n"
+    "output byte o_byte;\n"
+    "output chandle o_chandle;\n"
+    "output event o_event;\n"
+    "output int o_int;\n"
+    "output integer o_inte;\n"
+    "output longint o_longint;\n"
+    "output real o_real;\n"
+    "output realtime o_realtime;\n"
+    "output shortint o_shortint;\n"
+    "output shortreal o_shortreal;\n"
+    "output string o_string;\n"
+    "output time o_time;\n"
+    "endmodule\n",
+    "module t (\n"
+    "input bit i_bit,\n"
+    "input byte i_byte,\n"
+    "input chandle i_chandle,\n"
+    "input event i_event,\n"
+    "input int i_int,\n"
+    "input integer i_inte,\n"
+    "input longint i_longint,\n"
+    "input real i_real,\n"
+    "input realtime i_realtime,\n"
+    "input shortint i_shortint,\n"
+    "input shortreal i_shortreal,\n"
+    "input string i_string,\n"
+    "input time i_time,\n"
+    "output bit o_bit,\n"
+    "output byte o_byte,\n"
+    "output chandle o_chandle,\n"
+    "output event o_event,\n"
+    "output int o_int,\n"
+    "output integer o_inte,\n"
+    "output longint o_longint,\n"
+    "output real o_real,\n"
+    "output realtime o_realtime,\n"
+    "output shortint o_shortint,\n"
+    "output shortreal o_shortreal,\n"
+    "output string o_string,\n"
+    "output time o_time);\n"
+    "endmodule\n",
     "module zoom (a, co);\n"
     "input bus_type a;\n"
     "output bus_type [3:0] co;\n"

verible/verilog/parser/verilog.y

diff --git a/verible/verilog/parser/verilog.y b/verible/verilog/parser/verilog.y
index ef746fd..f1c24a8 100644
--- a/verible/verilog/parser/verilog.y
+++ b/verible/verilog/parser/verilog.y
@@ -5633,6 +5633,37 @@
     { $$ = MakeTaggedNode(N::kModulePortDeclaration, $1,
                           MakeDataType($3, ForwardChildren($2), MakePackedDimensionsNode($4)),
                           $5, $6); }
+  | port_direction TK_bit signed_unsigned_opt decl_dimensions_opt
+    list_of_identifiers_unpacked_dimensions ';'
+    { $$ = MakeTaggedNode(N::kModulePortDeclaration, $1,
+                          MakeDataType(MakeTaggedNode(N::kDataTypePrimitive, $2, $3),
+                                       MakePackedDimensionsNode($4)),
+                          $5, $6); }
+  | port_direction integer_atom_type signed_unsigned_opt
+    list_of_identifiers_unpacked_dimensions ';'
+    { $$ = MakeTaggedNode(N::kModulePortDeclaration, $1,
+                          MakeDataType(MakeTaggedNode(N::kDataTypePrimitive, $2, $3)),
+                          $4, $5); }
+  | port_direction non_integer_type
+    list_of_identifiers_unpacked_dimensions ';'
+    { $$ = MakeTaggedNode(N::kModulePortDeclaration, $1,
+                          MakeDataType(MakeTaggedNode(N::kDataTypePrimitive, $2)),
+                          $3, $4); }
+  | port_direction TK_string
+    list_of_identifiers_unpacked_dimensions ';'
+    { $$ = MakeTaggedNode(N::kModulePortDeclaration, $1,
+                          MakeDataType(MakeTaggedNode(N::kDataTypePrimitive, $2)),
+                          $3, $4); }
+  | port_direction TK_event
+    list_of_identifiers_unpacked_dimensions ';'
+    { $$ = MakeTaggedNode(N::kModulePortDeclaration, $1,
+                          MakeDataType(MakeTaggedNode(N::kDataTypePrimitive, $2)),
+                          $3, $4); }
+  | port_direction TK_chandle
+    list_of_identifiers_unpacked_dimensions ';'
+    { $$ = MakeTaggedNode(N::kModulePortDeclaration, $1,
+                          MakeDataType(MakeTaggedNode(N::kDataTypePrimitive, $2)),
+                          $3, $4); }
   ;
 
 parameter_override