Add unit test for calling system functions without parentheses

Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>

verilog/formatting/formatter_test.cc

diff --git a/verilog/formatting/formatter_test.cc b/verilog/formatting/formatter_test.cc
index b0cf132..8f00b0a 100644
--- a/verilog/formatting/formatter_test.cc
+++ b/verilog/formatting/formatter_test.cc
@@ -3426,7 +3426,7 @@
      "  input  bit [7:0]       data_i   [],\n"
      "  output bit [7:0]       data_o   []\n"
      ");\n"},
-    {// module with system task call
+    {// module with system task call w or w/o parentheses
      "module m; initial begin #10 $display(\"foo\"); $display(\"bar\");"
      "end endmodule",
      "module m;\n"
@@ -3435,6 +3435,15 @@
      "    $display(\"bar\");\n"
      "  end\n"
      "endmodule\n"},
+    {// module with system task call
+     "module m; initial begin #10 $display; $display;"
+     "end endmodule",
+     "module m;\n"
+     "  initial begin\n"
+     "    #10 $display;\n"
+     "    $display;\n"
+     "  end\n"
+     "endmodule\n"},
 
     // interface test cases
     {// two interface declarations