Merge branch 'chipsalliance:master' into fix/2605
diff --git a/verible/verilog/formatting/formatter_test.cc b/verible/verilog/formatting/formatter_test.cc index aad3e60..4b50ab9 100644 --- a/verible/verilog/formatting/formatter_test.cc +++ b/verible/verilog/formatting/formatter_test.cc
@@ -128,6 +128,50 @@ RunFormatterTestCases40(kSmokeFormatterTestCases); } +// Regression for https://github.com/chipsalliance/verible/issues/2605: +// TIMESCALE_DIRECTIVE's EndOfLineComment handler used yyless(yyleng-1), +// which left `\r` in the comment token for CRLF files. Emitting that token +// plus a CRLF terminator produced `\r\r\n` and failed FormatEquivalent. +TEST(FormatterEndToEndTest, TimescaleCrlfEolComment) { + static constexpr FormatterTestCase kTestCases[] = { + // Next-line `//` comment after `timescale (the reduced issue case). + {"`timescale 1 ps / 1 ps\r\n" + "// hello\r\n" + "module m;\r\n" + "endmodule\r\n", + "`timescale 1 ps / 1 ps\r\n" + "// hello\r\n" + "module m;\r\n" + "endmodule\r\n"}, + // Same-line `//` comment on the `timescale directive. + {"`timescale 1 ps / 1 ps // hello\r\n" + "module m;\r\n" + "endmodule\r\n", + "`timescale 1 ps / 1 ps // hello\r\n" + "module m;\r\n" + "endmodule\r\n"}, + // LF control: this path already passed lexical verification. + {"`timescale 1 ps / 1 ps\n" + "// hello\n" + "module m;\n" + "endmodule\n", + "`timescale 1 ps / 1 ps\n" + "// hello\n" + "module m;\n" + "endmodule\n"}, + }; + FormatStyle style; + style.line_terminator = verible::LineTerminatorOptionStyle::kAuto; + for (const auto &test_case : kTestCases) { + VLOG(1) << "code-to-format:\n" << test_case.input << "<EOF>"; + std::ostringstream stream; + const auto status = + FormatVerilog(test_case.input, "<filename>", style, stream); + EXPECT_OK(status) << status.message(); + EXPECT_EQ(stream.str(), test_case.expected) << "code:\n" << test_case.input; + } +} + } // namespace } // namespace formatter } // namespace verilog
diff --git a/verible/verilog/parser/verilog-lexer_test.cc b/verible/verilog/parser/verilog-lexer_test.cc index b1f3788..23d8cda 100644 --- a/verible/verilog/parser/verilog-lexer_test.cc +++ b/verible/verilog/parser/verilog-lexer_test.cc
@@ -2035,6 +2035,24 @@ {'/', "/"}, {TK_TimeLiteral, "1ps"}, {TK_NEWLINE, "\n"}}, + // Issue #2605: CRLF `//` comments in TIMESCALE_DIRECTIVE must not keep + // `\r`. + {{DR_timescale, "`timescale"}, + {TK_SPACE, " "}, + {TK_TimeLiteral, "1ps"}, + {'/', "/"}, + {TK_TimeLiteral, "1ps"}, + {TK_NEWLINE, "\r\n"}, + {TK_EOL_COMMENT, "// hello"}, + {TK_NEWLINE, "\r\n"}}, + {{DR_timescale, "`timescale"}, + {TK_SPACE, " "}, + {TK_TimeLiteral, "1ps"}, + {'/', "/"}, + {TK_TimeLiteral, "1ps"}, + {TK_SPACE, " "}, + {TK_EOL_COMMENT, "// hello"}, + {TK_NEWLINE, "\r\n"}}, // TODO(b/134180314): lexer current drops tokens from pragma sections, // but instead emit the tokens and filter them out. // {{DR_pragma, "`pragma"}, " fragma", {TK_NEWLINE, "\n"}},
diff --git a/verible/verilog/parser/verilog.lex b/verible/verilog/parser/verilog.lex index 759fcc2..5c4cf3b 100644 --- a/verible/verilog/parser/verilog.lex +++ b/verible/verilog/parser/verilog.lex
@@ -990,7 +990,13 @@ return TK_COMMENT_BLOCK; } {EndOfLineComment} { - yyless(yyleng-1); /* return \n to input stream */ + // Match IN_EOL_COMMENT: CRLF is a two-character terminator. Using + // yyless(yyleng-1) left `\r` in the comment token, so the formatter + // emitted `\r\r\n` after `timescale comments (issue #2605, PR #2371). + if (yyleng >= 2 && yytext[yyleng - 2] == '\r') + yyless(yyleng - 2); /* return \r\n to input stream */ + else + yyless(yyleng - 1); /* return \n to input stream */ UpdateLocation(); return TK_EOL_COMMENT; }