Sign in
foss-fpga-tools
/
third_party
/
verible
/
67b8fe74e31f81ac1d1fc943997f049a19e06673
/
.
/
verible
/
verilog
/
tools
/
lint
/
testdata
/
explicit_begin.sv
blob: 3aadad445b602d47414fb3455bdcb356c0aa265f [
file
]
module
explicit_begin
();
always_comb
a
=
1
;
endmodule
