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foss-fpga-tools
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third_party
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verible
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67b8fe74e31f81ac1d1fc943997f049a19e06673
/
.
/
verible
/
verilog
/
tools
/
lint
/
testdata
/
legacy_genvar_declaration.sv
blob: f041777fa724751a1bf1d7b4a11e13325ec813e3 [
file
]
// verilog_syntax: parse-as-module-body
genvar k
;
for
(
k
=
0
;
k
<
FooParam
;
k
++)
begin
:
gen_loop
// code
end
