Add private TODO for next formatter volunteer issues

Track #2008, #886, and #2352 as follow-up work after the current
formatter PRs land.

TODO.md

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+# Kalen's TODO File
+
+This is Kalen's private TODO file. Don't attempt to upstream this.
+
+## Formatter issues to volunteer
+
+These are the next three issues to take after the current formatter PRs land
+([#2545](https://github.com/chipsalliance/verible/pull/2545),
+[#2543](https://github.com/chipsalliance/verible/pull/2543),
+[#2546](https://github.com/chipsalliance/verible/pull/2546),
+[#2548](https://github.com/chipsalliance/verible/pull/2548)).
+
+Samples were re-run on `origin/master` (`1ea007ec`, `v0.0-4148-g1ea007ec`).
+
+### 1. Crash on `wire signed` — [#2008](https://github.com/chipsalliance/verible/issues/2008)
+
+Also covers [#2474](https://github.com/chipsalliance/verible/issues/2474) and
+likely [#2063](https://github.com/chipsalliance/verible/issues/2063).
+
+The formatter **aborts** on `input wire signed [...]`. Five-line sample, same
+`tree-unwrapper.cc` CHECK. Highest new-issue value: crash, tiny repro, one family.
+
+Claim **#2008** and mark #2474 / #2063 as duplicates once they share the same abort.
+
+### 2. Long function header drops code — [#886](https://github.com/chipsalliance/verible/issues/886)
+
+Wrapping a long function header **drops the function parameters**. Still happens
+on current master: the formatted output is not even valid SystemVerilog. Worse
+than a style bug.
+
+### 3. Spaces inserted in `*nix` paths — [#2352](https://github.com/chipsalliance/verible/issues/2352)
+
+Turns `` `PATH_MY_MODULE/src/config_class.sv `` into
+`` `PATH_MY_MODULE / src / config_class.sv ``, which **does not compile**.
+Small, well-scoped.