Merge pull request #2610 from wsnyder/modport

Fix space before modport explicit port name

verible/verilog/formatting/formatter_class_package_test.cc

diff --git a/verible/verilog/formatting/formatter_class_package_test.cc b/verible/verilog/formatting/formatter_class_package_test.cc
index 0c5e067..ee45c51 100644
--- a/verible/verilog/formatting/formatter_class_package_test.cc
+++ b/verible/verilog/formatting/formatter_class_package_test.cc
@@ -96,6 +96,18 @@
         "endinterface\n",
     },
     {
+        // Keep space before explicit modport port name
+        "interface\tfoo  ;"
+        "modport mp1(input  .a(sig), output  .b(sig));"
+        "endinterface",
+        "interface foo;\n"
+        "  modport mp1(\n"
+        "      input .a(sig),\n"
+        "      output .b(sig)\n"
+        "  );\n"
+        "endinterface\n",
+    },
+    {
         // interface with long modport port names
         "interface\tfoo_if  ;"
         "modport  mp1\t( output a_long_output, input detailed_input_name);"

verible/verilog/formatting/token-annotator.cc

diff --git a/verible/verilog/formatting/token-annotator.cc b/verible/verilog/formatting/token-annotator.cc
index fc6d2f0..2e5b209 100644
--- a/verible/verilog/formatting/token-annotator.cc
+++ b/verible/verilog/formatting/token-annotator.cc
@@ -282,6 +282,12 @@
 
   // TODO(fangism): Never insert trailing spaces before a newline.
 
+  // Modport port name separator, e.g. "input .a("
+  if (right.TokenEnum() == '.' &&
+      right_context.IsInside(NodeEnum::kModportSimplePort)) {
+    return {1, "Space before modport explicit port name '.'"};
+  }
+
   // Hierarchy examples: "a.b", "a::b"
   if (left.format_token_enum == FormatTokenType::hierarchy ||
       right.format_token_enum == FormatTokenType::hierarchy) {

verible/verilog/formatting/token-annotator_test.cc

diff --git a/verible/verilog/formatting/token-annotator_test.cc b/verible/verilog/formatting/token-annotator_test.cc
index 2adf936..c54cacd 100644
--- a/verible/verilog/formatting/token-annotator_test.cc
+++ b/verible/verilog/formatting/token-annotator_test.cc
@@ -2753,6 +2753,24 @@
           {1, SpacingOptions::kUndecided},
       },
 
+      // Modport explicit port name, e.g. "input .a(sig)"
+      {
+          DefaultStyle,
+          {TK_input, "input"},
+          {'.', "."},
+          {/* any context */},
+          {NodeEnum::kModportSimplePort},
+          {1, SpacingOptions::kUndecided},
+      },
+      {
+          DefaultStyle,
+          {TK_output, "output"},
+          {'.', "."},
+          {/* any context */},
+          {NodeEnum::kModportSimplePort},
+          {1, SpacingOptions::kUndecided},
+      },
+
       // Handle '->' as a unary prefix expression.
       {
           DefaultStyle,