Merge pull request #2608 from kbrunham-intel/fix/2607

Fix CRLF macro definitions failing formatter convergence

verible/verilog/formatting/BUILD

diff --git a/verible/verilog/formatting/BUILD b/verible/verilog/formatting/BUILD
index 6e4782e..491a5cf 100644
--- a/verible/verilog/formatting/BUILD
+++ b/verible/verilog/formatting/BUILD
@@ -301,6 +301,7 @@
         ":format-style",
         ":formatter",
         ":formatter-test-utils",
+        "//verible/common/formatting:basic-format-style",
         "//verible/common/util:logging",
         "@googletest//:gtest",
         "@googletest//:gtest_main",

verible/verilog/formatting/formatter_issue_regression_test.cc

diff --git a/verible/verilog/formatting/formatter_issue_regression_test.cc b/verible/verilog/formatting/formatter_issue_regression_test.cc
index 9490a88..4dcbad5 100644
--- a/verible/verilog/formatting/formatter_issue_regression_test.cc
+++ b/verible/verilog/formatting/formatter_issue_regression_test.cc
@@ -73,6 +73,23 @@
   }
 }
 
+// Regression for https://github.com/chipsalliance/verible/issues/2607:
+// A CRLF macro definition must keep a single line terminator so formatting
+// converges.
+TEST(FormatterEndToEndTest, DefineCrlfConverges) {
+  static constexpr FormatterTestCase kTestCases[] = {
+      {"`define A x.y\r\n"
+       "module m;\r\n"
+       "endmodule\r\n",
+       "`define A x.y\r\n"
+       "module m;\r\n"
+       "endmodule\r\n"},
+  };
+  FormatStyle style;
+  style.line_terminator = verible::LineTerminatorOptionStyle::kAuto;
+  RunFormatterTestCases(style, kTestCases);
+}
+
 // Regression for https://github.com/chipsalliance/verible/issues/2544:
 // Wrapping a $bits(...)'(...) cast may leave `MACRO at EOL, reclassifying
 // MacroIdentifier as MacroIdItem. FormatEquivalent must accept that, and

verible/verilog/parser/verilog-lexer_test.cc

diff --git a/verible/verilog/parser/verilog-lexer_test.cc b/verible/verilog/parser/verilog-lexer_test.cc
index b1f3788..e23b911 100644
--- a/verible/verilog/parser/verilog-lexer_test.cc
+++ b/verible/verilog/parser/verilog-lexer_test.cc
@@ -472,6 +472,12 @@
 static std::initializer_list<LexerTestData> kMacroDefineTests = {
     {{PP_define, "`define"},
      {TK_SPACE, " "},
+     {PP_Identifier, "A"},
+     {TK_SPACE, " "},
+     {PP_define_body, "x.y"},
+     {TK_NEWLINE, "\r\n"}},
+    {{PP_define, "`define"},
+     {TK_SPACE, " "},
      {PP_Identifier, "FOO"},
      {PP_define_body, ""},
      {TK_NEWLINE, "\n"}},

verible/verilog/parser/verilog.lex

diff --git a/verible/verilog/parser/verilog.lex b/verible/verilog/parser/verilog.lex
index 759fcc2..3afd55e 100644
--- a/verible/verilog/parser/verilog.lex
+++ b/verible/verilog/parser/verilog.lex
@@ -1229,7 +1229,10 @@
     yymore();
   }
   {DiscontinuedLine} {
-    yyless(yyleng-1);  /* return \n to input stream */
+    if (yyleng >= 2 && yytext[yyleng - 2] == '\r')
+      yyless(yyleng - 2);  /* return \r\n to input stream */
+    else
+      yyless(yyleng - 1);  /* return \n to input stream */
     UpdateLocation();
     yy_pop_state();
     /* Return a dummy token so the Location range of the definition (@$) spans