verilog/tools/lint/testdata/port_name_suffix.sv - third_party/verible - Git at Google


            
            // Expects module port 'hello_world' to follow end with _i

            
            module port_name_suffix(input bit hello_world);

            
            endmodule
	// Expects module port 'hello_world' to follow end with _i
	module port_name_suffix(input bit hello_world);
	endmodule