Move #2605 formatter regression into the issue test file.

Keep formatter_test.cc as the #2602 smoke suite and place the GitHub
issue cases in formatter_issue_regression_test.cc.

verible/verilog/formatting/formatter_issue_regression_test.cc

diff --git a/verible/verilog/formatting/formatter_issue_regression_test.cc b/verible/verilog/formatting/formatter_issue_regression_test.cc
index 8f1fcef..3775053 100644
--- a/verible/verilog/formatting/formatter_issue_regression_test.cc
+++ b/verible/verilog/formatting/formatter_issue_regression_test.cc
@@ -314,6 +314,43 @@
     EXPECT_EQ(stream.str(), test_case.expected) << "code:\n" << test_case.input;
   }
 }
+
+// Regression for https://github.com/chipsalliance/verible/issues/2605:
+// TIMESCALE_DIRECTIVE's EndOfLineComment handler used yyless(yyleng-1),
+// which left `\r` in the comment token for CRLF files. Emitting that token
+// plus a CRLF terminator produced `\r\r\n` and failed FormatEquivalent.
+TEST(FormatterEndToEndTest, TimescaleCrlfEolComment) {
+  static constexpr FormatterTestCase kTestCases[] = {
+      // Next-line `//` comment after `timescale (the reduced issue case).
+      {"`timescale 1 ps / 1 ps\r\n"
+       "// hello\r\n"
+       "module m;\r\n"
+       "endmodule\r\n",
+       "`timescale 1 ps / 1 ps\r\n"
+       "// hello\r\n"
+       "module m;\r\n"
+       "endmodule\r\n"},
+      // Same-line `//` comment on the `timescale directive.
+      {"`timescale 1 ps / 1 ps // hello\r\n"
+       "module m;\r\n"
+       "endmodule\r\n",
+       "`timescale 1 ps / 1 ps  // hello\r\n"
+       "module m;\r\n"
+       "endmodule\r\n"},
+      // LF control: this path already passed lexical verification.
+      {"`timescale 1 ps / 1 ps\n"
+       "// hello\n"
+       "module m;\n"
+       "endmodule\n",
+       "`timescale 1 ps / 1 ps\n"
+       "// hello\n"
+       "module m;\n"
+       "endmodule\n"},
+  };
+  FormatStyle style;
+  style.line_terminator = verible::LineTerminatorOptionStyle::kAuto;
+  RunFormatterTestCases(style, kTestCases);
+}
 }  // namespace
 }  // namespace formatter
 }  // namespace verilog

verible/verilog/formatting/formatter_test.cc

diff --git a/verible/verilog/formatting/formatter_test.cc b/verible/verilog/formatting/formatter_test.cc
index 4b50ab9..aad3e60 100644
--- a/verible/verilog/formatting/formatter_test.cc
+++ b/verible/verilog/formatting/formatter_test.cc
@@ -128,50 +128,6 @@
   RunFormatterTestCases40(kSmokeFormatterTestCases);
 }
 
-// Regression for https://github.com/chipsalliance/verible/issues/2605:
-// TIMESCALE_DIRECTIVE's EndOfLineComment handler used yyless(yyleng-1),
-// which left `\r` in the comment token for CRLF files. Emitting that token
-// plus a CRLF terminator produced `\r\r\n` and failed FormatEquivalent.
-TEST(FormatterEndToEndTest, TimescaleCrlfEolComment) {
-  static constexpr FormatterTestCase kTestCases[] = {
-      // Next-line `//` comment after `timescale (the reduced issue case).
-      {"`timescale 1 ps / 1 ps\r\n"
-       "// hello\r\n"
-       "module m;\r\n"
-       "endmodule\r\n",
-       "`timescale 1 ps / 1 ps\r\n"
-       "// hello\r\n"
-       "module m;\r\n"
-       "endmodule\r\n"},
-      // Same-line `//` comment on the `timescale directive.
-      {"`timescale 1 ps / 1 ps // hello\r\n"
-       "module m;\r\n"
-       "endmodule\r\n",
-       "`timescale 1 ps / 1 ps  // hello\r\n"
-       "module m;\r\n"
-       "endmodule\r\n"},
-      // LF control: this path already passed lexical verification.
-      {"`timescale 1 ps / 1 ps\n"
-       "// hello\n"
-       "module m;\n"
-       "endmodule\n",
-       "`timescale 1 ps / 1 ps\n"
-       "// hello\n"
-       "module m;\n"
-       "endmodule\n"},
-  };
-  FormatStyle style;
-  style.line_terminator = verible::LineTerminatorOptionStyle::kAuto;
-  for (const auto &test_case : kTestCases) {
-    VLOG(1) << "code-to-format:\n" << test_case.input << "<EOF>";
-    std::ostringstream stream;
-    const auto status =
-        FormatVerilog(test_case.input, "<filename>", style, stream);
-    EXPECT_OK(status) << status.message();
-    EXPECT_EQ(stream.str(), test_case.expected) << "code:\n" << test_case.input;
-  }
-}
-
 }  // namespace
 }  // namespace formatter
 }  // namespace verilog