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foss-fpga-tools
/
third_party
/
verible
/
c428b43c153fa0708394d76824d00a0e94801683
/
.
/
verilog
/
tools
/
lint
/
testdata
/
generate_label_module.sv
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module
generate_label_module
;
// verilog_lint: waive legacy-generate-region
generate
if
(
foo
)
begin
baz bam
;
end
endgenerate
endmodule
