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verible
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d6f06e4e4eeb838cb48e07546a30fa39c8399e08
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verilog
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tools
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lint
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testdata
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always_comb_module.sv
blob: 4bfca271b5753deca6f5513787c7e00de5d2d5cd [
file
]
module
always_comb_module
;
always
@*
begin
a
=
b
+
c
;
end
endmodule