Deploying to gh-pages from @ chipsalliance/verible@682a1d502d749ced074537a14aba4f15076dd668 🚀
diff --git a/README.md b/README.md index f76372c..960e843 100644 --- a/README.md +++ b/README.md
@@ -175,8 +175,9 @@ Verible's code base is written in C++. -To build, you need the [bazel] build system (Min version 7) and a C++20 -compatible compiler. +To build, you need the [bazel] build system (get it from +[bazel install][bazel-install] if not already on your system) and a +C++20 compatible compiler. Use your package manager to install the dependencies; on a system with the nix package manager simply run `nix-shell` to get a build environment. @@ -202,6 +203,8 @@ bazel build -c opt --config=create_static_linked_executables //... ``` +See [Installation](#installation-1) for install. + ### Optionally using local flex/bison for build Flex and Bison, that are needed for the parser generation, are compiled as part @@ -286,6 +289,7 @@ [UHDM] format. If you are interested in collaborating, contact us. [bazel]: https://bazel.build/ +[bazel-install]: https://bazel.build/install [SV-LRM]: https://ieeexplore.ieee.org/document/8299595 [lint-rule-list]: https://chipsalliance.github.io/verible/lint.html [github-lint-action]: https://github.com/chipsalliance/verible-linter-action
diff --git a/index.md b/index.md index c2aa217..86d4d78 100644 --- a/index.md +++ b/index.md
@@ -58,4 +58,4 @@ ## Version -Generated on 2026-09-09 07:14:49 +0200 from [a5e3878](https://github.com/google/verible/commit/a5e38787b696a1834ec891995f6152439a3fd3ed) +Generated on 2026-09-10 09:41:13 +0200 from [682a1d5](https://github.com/google/verible/commit/682a1d502d749ced074537a14aba4f15076dd668)
diff --git a/lint.md b/lint.md index 6849059..e18c5b4 100644 --- a/lint.md +++ b/lint.md
@@ -144,7 +144,10 @@ Enabled by default: true ### generate-label-prefix -Checks that every generate block label starts with g_ or gen_. See [Style: generate-constructs]. +Checks that every generate block label matches the regex defined by style_regex. The default regex requires labels to start with g_ or gen_. Refer to https://github.com/chipsalliance/verible/tree/master/verilog/tools/lint#readme for more detail on verible regex patterns. See [Style: generate-constructs]. + +##### Parameter + * `style_regex` Default: `(g_|gen_).*` A regex used to check generate label style. Enabled by default: true @@ -382,4 +385,4 @@ ## Version -Generated on 2026-09-09 07:14:49 +0200 from [a5e3878](https://github.com/google/verible/commit/a5e38787b696a1834ec891995f6152439a3fd3ed) +Generated on 2026-09-10 09:41:13 +0200 from [682a1d5](https://github.com/google/verible/commit/682a1d502d749ced074537a14aba4f15076dd668)
diff --git a/verilog_format.md b/verilog_format.md index 2442983..b485535 100644 --- a/verilog_format.md +++ b/verilog_format.md
@@ -53,6 +53,11 @@ {align,flush-left,preserve,infer}); default: infer; --class_member_variable_alignment (Format class member variables: {align,flush-left,preserve,infer}); default: infer; + --class_parameter_space (If true, keep/insert a space before '#' in a + classparameterized typedef, e.g. "typedef my_class #(.P(P)) my_class_t;". + If false (default), no space is inserted, matching the convention used for + IEEE parameterized class instantiations, e.g. + "type#(params...)::method(...)".); default: false; --compact_indexing_and_selections (Use compact binary expressions inside indexing / bit selection operators); default: true; --distribution_items_alignment (Align distribution items: @@ -143,4 +148,4 @@ ## Version -Generated on 2026-09-09 07:14:49 +0200 from [a5e3878](https://github.com/google/verible/commit/a5e38787b696a1834ec891995f6152439a3fd3ed) +Generated on 2026-09-10 09:41:13 +0200 from [682a1d5](https://github.com/google/verible/commit/682a1d502d749ced074537a14aba4f15076dd668)
diff --git a/verilog_lint.md b/verilog_lint.md index eeef0e4..8251044 100644 --- a/verilog_lint.md +++ b/verilog_lint.md
@@ -215,7 +215,10 @@ Enabled by default: true ### generate-label-prefix -Checks that every generate block label starts with g_ or gen_. See [Style: generate-constructs]. +Checks that every generate block label matches the regex defined by style_regex. The default regex requires labels to start with g_ or gen_. Refer to https://github.com/chipsalliance/verible/tree/master/verilog/tools/lint#readme for more detail on verible regex patterns. See [Style: generate-constructs]. + +##### Parameter + * `style_regex` Default: `(g_|gen_).*` A regex used to check generate label style. Enabled by default: true @@ -453,4 +456,4 @@ ## Version -Generated on 2026-09-09 07:14:49 +0200 from [a5e3878](https://github.com/google/verible/commit/a5e38787b696a1834ec891995f6152439a3fd3ed) +Generated on 2026-09-10 09:41:13 +0200 from [682a1d5](https://github.com/google/verible/commit/682a1d502d749ced074537a14aba4f15076dd668)
diff --git a/verilog_syntax.md b/verilog_syntax.md index b27ca3c..8c8440e 100644 --- a/verilog_syntax.md +++ b/verilog_syntax.md
@@ -51,4 +51,4 @@ ## Version -Generated on 2026-09-09 07:14:49 +0200 from [a5e3878](https://github.com/google/verible/commit/a5e38787b696a1834ec891995f6152439a3fd3ed) +Generated on 2026-09-10 09:41:13 +0200 from [682a1d5](https://github.com/google/verible/commit/682a1d502d749ced074537a14aba4f15076dd668)