Merge origin/master into fix/2539

Keep PortListCommentWithLineContinuationDoesNotAbort and drop this
branch's production alignment changes in favor of master's #2530 fix.

verible/verilog/formatting/formatter_test.cc

diff --git a/verible/verilog/formatting/formatter_test.cc b/verible/verilog/formatting/formatter_test.cc
index dce9f05..fbcf9b5 100644
--- a/verible/verilog/formatting/formatter_test.cc
+++ b/verible/verilog/formatting/formatter_test.cc
@@ -19380,6 +19380,32 @@
   }
 }
 
+// Regression for https://github.com/chipsalliance/verible/issues/2539:
+// A // comment followed by a line-continuation `\` before aligned ports must
+// not abort in align.h, and must keep the comment on its own line.
+TEST(FormatterEndToEndTest, PortListCommentWithLineContinuationDoesNotAbort) {
+  static constexpr std::string_view kInput =
+      "module m (\n"
+      "//\\\n"
+      "input a\n"
+      ",input b\n"
+      ");\n"
+      "endmodule\n";
+  FormatStyle style;
+  std::ostringstream stream;
+  const auto status = FormatVerilog(kInput, "<filename>", style, stream);
+  EXPECT_OK(status) << status.message();
+  const std::string out = stream.str();
+  // Must not glue the line-continuation onto the following port declaration.
+  EXPECT_THAT(out, testing::Not(testing::HasSubstr("//\\  input")));
+  EXPECT_THAT(out, testing::HasSubstr("//\\"));
+  EXPECT_THAT(out, testing::HasSubstr("input a"));
+  EXPECT_THAT(out, testing::HasSubstr("input b"));
+  EXPECT_THAT(out, testing::HasSubstr("endmodule"));
+  // Comment line and first port remain on separate lines.
+  EXPECT_THAT(out, testing::ContainsRegex(R"(//\\\n\s*input a)"));
+}
+
 // Regression for https://github.com/chipsalliance/verible/issues/2540:
 // Trailing EOL comment after `end` before `else if` must not change whether
 // the else-if assignment stays on one line across re-format (convergence).