Sign in
foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
031e8d9a9ab5c0ccd1a84ad2d7e79d509f0eba6d
/
.
/
libsdcparse
/
test_sdcs
/
test13.sdc
blob: b2c1cd9f6c2d2fc7e3a2198af2a2062c3259892e [
file
] [
log
] [
blame
]
set_clock_latency
-
source
-
late
3.4
[
get_clocks clk1
]
set_clock_latency
-
source
-
late
3.4
[
get_clocks clk
*]
set_clock_latency
-
source
-
early
3.4
[
get_clocks
{
clk2
}]
set_clock_latency
-
source
3.4
[
get_clocks
{
clk3
}]
