Sign in
foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
031e8d9a9ab5c0ccd1a84ad2d7e79d509f0eba6d
/
.
/
libsdcparse
/
test_sdcs
/
test8.sdc
blob: 8cad4e8c9f3c737d0aa71063c8d97ab9fbf33e60 [
file
] [
log
] [
blame
]
create_clock
-
period
1.0
*
_pll