ODIN_II/regression_test/benchmark/task/full/task.conf

########################
# full benchmarks config
########################

regression_params=--disable_parallel_jobs
script_synthesis_params=--time_limit 3600s
script_simulation_params=--time_limit 3600s
simulation_params= -L reset rst -H we

# setup the architecture
arch_dir=../vtr_flow/arch/timing

# arch_list_add=k6_N10_mem32K_40nm.xml
arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml

# setup the circuits
circuit_dir=regression_test/benchmark/verilog/full

circuit_list_add=cf_fft_256_8.v
circuit_list_add=mcml.v
circuit_list_add=bm_DL_four_bit_adder_continuous_assign_using_vectors.v
circuit_list_add=oc54_cpu.v
circuit_list_add=LU8PEEng.v
circuit_list_add=cf_fir_3_8_8.v
circuit_list_add=diffeq2.v
circuit_list_add=sha.v
circuit_list_add=CRC33_D264.v
circuit_list_add=cf_cordic_v_18_18_18.v
circuit_list_add=iir_no_combinational.v
circuit_list_add=mkPktMerge.v
circuit_list_add=stereovision3.v
circuit_list_add=stereovision1.v
circuit_list_add=fir_scu_rtl_restructured_for_cmm_exp.v
circuit_list_add=diffeq1.v
circuit_list_add=ansiportlist.v
circuit_list_add=blob_merge.v
circuit_list_add=ansiportlist_2.v
circuit_list_add=stereovision2.v
circuit_list_add=cf_cordic_v_8_8_8.v
circuit_list_add=stereovision0.v
circuit_list_add=cf_fir_24_16_16.v
circuit_list_add=iir1.v
circuit_list_add=paj_framebuftop_hierarchy_no_mem_no_combinational.v
circuit_list_add=binops.v
circuit_list_add=ch_intrinsics.v
circuit_list_add=bm_sfifo_rtl.v
circuit_list_add=memory_controller.v
circuit_list_add=bm_base_memory.v
circuit_list_add=matmul.v