ODIN_II/regression_test/benchmark/task/large/task.conf

########################
# large benchmarks config
########################

regression_params=--disable_simulation --disable_parallel_jobs
script_synthesis_params=--limit_ressource --time_limit 3600s
script_simulation_params=--limit_ressource --time_limit 3600s

# setup the architecture
arch_dir=../vtr_flow/arch/timing

arch_list_add=k6_N10_mem32K_40nm.xml
#arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml

# setup the circuits
circuit_dir=regression_test/benchmark/verilog/large

circuit_list_add=mac2.v
circuit_list_add=LU32PEEng.v
circuit_list_add=LargeRam.v
circuit_list_add=mkSMAdapter4B.v
circuit_list_add=spree.v
circuit_list_add=boundtop.v
circuit_list_add=arm_core.v
circuit_list_add=or1200.v
circuit_list_add=paj_framebuftop_hierarchy_no_mem.v
circuit_list_add=mac1.v
circuit_list_add=des_perf.v
circuit_list_add=raygentop.v
circuit_list_add=mkDelayWorker32B.v
circuit_list_add=sv_chip1_hierarchy_no_mem.v
circuit_list_add=paj_top_hierarchy_no_mem.v
circuit_list_add=des_area.v
circuit_list_add=sv_chip0_hierarchy_no_mem.v
circuit_list_add=paj_boundtop_hierarchy_no_mem.v
circuit_list_add=LU64PEEng.v
circuit_list_add=sv_chip3_hierarchy_no_mem.v
circuit_list_add=bgm.v
circuit_list_add=sv_chip2_hierarchy_no_mem.v
circuit_list_add=paj_raygentop_hierarchy_no_mem.v
circuit_list_add=iir.v