| .. Verilog-to-Routing documentation master file, created by |
| sphinx-quickstart on Fri Jan 22 10:08:21 2016. |
| You can adapt this file completely to your liking, but it should at least |
| contain the root `toctree` directive. |
| |
| Welcome to Verilog-to-Routing's documentation! |
| ============================================== |
| |
| Form more information on the Verilog-to-Routing (VTR) project see :ref:`vtr` and :ref:`vtr_cad_flow`. |
| |
| For documentation and tutorials on the FPGA architecture description langauge see: :ref:`fpga_architecture_description`. |
| |
| For more specific documentation about VPR see :ref:`vpr`. |
| |
| .. toctree:: |
| :maxdepth: 2 |
| :caption: Usage |
| |
| vtr/index |
| arch/index |
| vpr/index |
| odin/index |
| abc/index |
| tutorials/index |
| utils/index |
| |
| .. toctree:: |
| :maxdepth: 2 |
| :caption: Development |
| |
| dev/index |
| |
| .. toctree:: |
| :maxdepth: 2 |
| :caption: Appendix |
| |
| contact |
| glossary |
| zreferences |
| |
| Indices and tables |
| ================== |
| |
| * :ref:`genindex` |
| * :ref:`search` |
| |
