doc/src/vpr/basic_flow.rst

Basic flow
==========

The Place and Route process in VPR consists of several steps:

- Packing (combinines primitives into complex blocks)
- Placment (places complex blocks within the FPGA grid)
- Routing (determines interconnections between blocks)
- Analysis (analyzes the implementation)

Each of these steps provides additional configuration options that can be used to customize the whole process.

Packing
-------

The packing algorithm tries to combine primitive netlist blocks (e.g. LUTs, FFs) into groups, called Complex Blocks (as specified in the :ref:`FPGA architecture file <arch_complex_blocks>`).
The results from the packing process are written into a ``.net`` file.
It contains a description of complex blocks with their inputs, outputs, used clocks and relations to other signals.
It can be useful in analyzing how VPR packs primitives together.

A detailed description of the ``.net`` file format can be found in the :ref:`vpr_pack_file` section.

Placement
---------

This step assigns a location to the Complex Blocks (produced by packing) with the FPGA grid, while optimizing for wirelength and timing.
The output from this step is written to the ``.place`` file, which contains the physical location of the blocks from the ``.net`` file.

The file has the following format:

.. code-block:: none

    block_name    x        y   subblock_number

where ``x`` and ``y`` are positions in the VPR grid and ``block_name`` comes from the ``.net`` file.

Example of a placing file:

.. code-block:: none

    Netlist_File: top.net Netlist_ID: SHA256:ce5217d251e04301759ee5a8f55f67c642de435b6c573148b67c19c5e054c1f9
    Array size: 149 x 158 logic blocks

    #block name	x	y	subblk	block number
    #----------	--	--	------	------------
    $auto$alumacc.cc:474:replace_alu$24.slice[1].carry4_full	53	32	0	#0
    $auto$alumacc.cc:474:replace_alu$24.slice[2].carry4_full	53	31	0	#1
    $auto$alumacc.cc:474:replace_alu$24.slice[3].carry4_full	53	30	0	#2
    $auto$alumacc.cc:474:replace_alu$24.slice[4].carry4_full	53	29	0	#3
    $auto$alumacc.cc:474:replace_alu$24.slice[5].carry4_full	53	28	0	#4
    $auto$alumacc.cc:474:replace_alu$24.slice[6].carry4_part	53	27	0	#5
    $auto$alumacc.cc:474:replace_alu$24.slice[0].carry4_1st_full	53	33	0	#6
    out:LD7		9	5	0	#7
    clk		42	26	0	#8
    $false		35	26	0	#9

A detailed description of the ``.place`` file format can be found in the :ref:`vpr_place_file` section.

Routing
-------

This step determines how to connect the placed Complex Blocks together, according to the netlist connectivity and the routing resources of the FPGA chip.
The router uses a Routing Resource (RR) Graph :cite:`betz_arch_cad` to represent the FPGA's available routing resources.
The RR graph can be created in two ways:

#. Automatically generated by VPR from the :ref:`FPGA architecture description <arch_reference>` :cite:`betz_automatic_generation_of_fpga_routing`, or
#. Loaded from an external :ref:`RR graph file <vpr_route_resource_file>`.

The output of routing is written into a ``.route`` file.
The file describes each connection from input to its output through different routing resources of the FPGA.
Each net starts with a ``SOURCE`` node and ends in a ``SINK`` node, potentially passing through complex block input/output pins (``IPIN``/``OPIN`` nodes) and horizontal/vertical routing wires (``CHANX``/``CHANY`` nodes).
The pair of numbers in round brackets provides information on the (x, y) resource location on the VPR grid.
The additional field provides information about the specific node.

An example routing file could look as follows:

.. code-block:: none

    Placement_File: top.place Placement_ID: SHA256:88d45f0bf7999e3f9331cdfd3497d0028be58ffa324a019254c2ae7b4f5bfa7a
    Array size: 149 x 158 logic blocks.

    Routing:

    Net 0 (counter[4])

    Node:	203972	SOURCE (53,32)  Class: 40  Switch: 0
    Node:	204095	  OPIN (53,32)  Pin: 40   BLK-TL-SLICEL.CQ[0] Switch: 189
    Node:	1027363	 CHANY (52,32)  Track: 165  Switch: 7
    Node:	601704	 CHANY (52,32)  Track: 240  Switch: 161
    Node:	955959	 CHANY (52,32) to (52,33)  Track: 90  Switch: 130
    Node:	955968	 CHANY (52,32)  Track: 238  Switch: 128
    Node:	955976	 CHANY (52,32)  Track: 230  Switch: 131
    Node:	601648	 CHANY (52,32)  Track: 268  Switch: 7
    Node:	1027319	 CHANY (52,32)  Track: 191  Switch: 183
    Node:	203982	  IPIN (53,32)  Pin: 1   BLK-TL-SLICEL.A2[0] Switch: 0
    Node:	203933	  SINK (53,32)  Class: 1  Switch: -1

   Net 1 ($auto$alumacc.cc:474:replace_alu$24.O[6])
   ...

A detailed description of the ``.route`` file format can be found in the :ref:`vpr_route_file` section.

Analysis
--------
This step analyzes the resulting implementation, producing information about:
 - Resource usage (e.g. block types, wiring)
 - Timing (e.g. critical path delays and timing paths)
 - Power (e.g. total power used, power broken down by blocks)

Note that VPR's analysis can be used independently of VPR's optimization stages, so long as the appropriate ``.net``/``.place``/``.route`` files are available.