| <!-- Architecture capture of the Xilinx XC6VLX240TFF1156 device, |
| based off of Eddie Hung's Verilog-to-Bitstream v2.1 |
| |
| Note that the routing architecture described here does not |
| reflect that of the real device. However the floorpland and block |
| architectures should be reasonably accurate. --> |
| <architecture> |
| <!-- ODIN II specific config --> |
| <models> |
| <model name="multiply"> |
| <input_ports> |
| <port name="a" combinational_sink_ports="p"/> |
| <port name="b" combinational_sink_ports="p"/> |
| </input_ports> |
| <output_ports> |
| <port name="p"/> |
| </output_ports> |
| </model> |
| <model name="single_port_ram"> |
| <input_ports> |
| <port name="we" clock="clk"/> |
| <port name="addr" clock="clk"/> |
| <port name="data" clock="clk"/> |
| <port name="clk" is_clock="1"/> |
| </input_ports> |
| <output_ports> |
| <port name="out" clock="clk"/> |
| </output_ports> |
| </model> |
| <model name="dual_port_ram"> |
| <input_ports> |
| <port name="we1" clock="clk"/> |
| <port name="we2" clock="clk"/> |
| <port name="addr1" clock="clk"/> |
| <port name="addr2" clock="clk"/> |
| <port name="data1" clock="clk"/> |
| <port name="data2" clock="clk"/> |
| <port name="clk" is_clock="1"/> |
| </input_ports> |
| <output_ports> |
| <port name="out1" clock="clk"/> |
| <port name="out2" clock="clk"/> |
| </output_ports> |
| </model> |
| <model name="adder"> |
| <input_ports> |
| <port name="a" combinational_sink_ports="cout sumout"/> |
| <port name="b" combinational_sink_ports="cout sumout"/> |
| <port name="cin" combinational_sink_ports="cout sumout"/> |
| </input_ports> |
| <output_ports> |
| <port name="cout"/> |
| <port name="sumout"/> |
| </output_ports> |
| </model> |
| <model name="xadder"> |
| <input_ports> |
| <port name="a_xor_b" combinational_sink_ports="sumout cout"/> |
| <port name="a_and_b" combinational_sink_ports="sumout cout"/> |
| <port name="cin" combinational_sink_ports="sumout cout"/> |
| </input_ports> |
| <output_ports> |
| <port name="cout"/> |
| <port name="sumout"/> |
| </output_ports> |
| </model> |
| <model name="bufgctrl"> |
| <input_ports> |
| <port name="i" combinational_sink_ports="o"/> |
| <port name="s" combinational_sink_ports="o"/> |
| <port name="ce" combinational_sink_ports="o"/> |
| <port name="ignore" combinational_sink_ports="o"/> |
| </input_ports> |
| <output_ports> |
| <port name="o"/> |
| </output_ports> |
| </model> |
| </models> |
| <tiles> |
| <tile name="IOB" capacity="2"> |
| <equivalent_sites> |
| <site pb_type="IOB"/> |
| </equivalent_sites> |
| <input name="O" num_pins="1"/> |
| <output name="I" num_pins="1"/> |
| <output name="GND_WIRE" num_pins="1"/> |
| <output name="VCC_WIRE" num_pins="1"/> |
| <fc in_type="abs" in_val="1" out_type="abs" out_val="1"/> |
| <pinlocations pattern="spread"/> |
| </tile> |
| <tile name="SLICEL" capacity="2"> |
| <equivalent_sites> |
| <site pb_type="SLICEL"/> |
| </equivalent_sites> |
| <input name="A6-1" num_pins="6" equivalent="full"/> |
| <input name="A6_VCCONLY" num_pins="1" equivalent="none"/> |
| <input name="AX" num_pins="1" equivalent="none"/> |
| <input name="B6-1" num_pins="6" equivalent="full"/> |
| <input name="B6_VCCONLY" num_pins="1" equivalent="none"/> |
| <input name="BX" num_pins="1" equivalent="none"/> |
| <input name="C6-1" num_pins="6" equivalent="full"/> |
| <input name="C6_VCCONLY" num_pins="1" equivalent="none"/> |
| <input name="CX" num_pins="1" equivalent="none"/> |
| <input name="D6-1" num_pins="6" equivalent="full"/> |
| <input name="D6_VCCONLY" num_pins="1" equivalent="none"/> |
| <input name="DX" num_pins="1" equivalent="none"/> |
| <input name="CIN" num_pins="1" equivalent="none"/> |
| <output name="A" num_pins="1" equivalent="none"/> |
| <output name="AQ" num_pins="1" equivalent="none"/> |
| <output name="AMUX" num_pins="1" equivalent="none"/> |
| <output name="B" num_pins="1" equivalent="none"/> |
| <output name="BQ" num_pins="1" equivalent="none"/> |
| <output name="BMUX" num_pins="1" equivalent="none"/> |
| <output name="C" num_pins="1" equivalent="none"/> |
| <output name="CQ" num_pins="1" equivalent="none"/> |
| <output name="CMUX" num_pins="1" equivalent="none"/> |
| <output name="D" num_pins="1" equivalent="none"/> |
| <output name="DQ" num_pins="1" equivalent="none"/> |
| <output name="DMUX" num_pins="1" equivalent="none"/> |
| <output name="COUT" num_pins="1" equivalent="none"/> |
| <output name="GND_WIRE" num_pins="1"/> |
| <output name="VCC_WIRE" num_pins="1"/> |
| <clock name="CLK" num_pins="1"/> |
| <fc in_type="abs" in_val="1" out_type="abs" out_val="1"> |
| <!-- Carry chain pins have no access to general routing --> |
| <fc_override port_name="CIN" fc_type="frac" fc_val="0"/> |
| <fc_override port_name="COUT" fc_type="frac" fc_val="0"/> |
| </fc> |
| <pinlocations pattern="spread"/> |
| </tile> |
| <tile name="DSP48E1" height="5" capacity="2"> |
| <equivalent_sites> |
| <site pb_type="DSP48E1"/> |
| </equivalent_sites> |
| <input name="A" num_pins="30"/> |
| <input name="B" num_pins="18"/> |
| <input name="CEA1" num_pins="1"/> |
| <input name="CEA2" num_pins="1"/> |
| <input name="CEB1" num_pins="1"/> |
| <input name="CEB2" num_pins="1"/> |
| <input name="CEM" num_pins="1"/> |
| <input name="CEP" num_pins="1"/> |
| <input name="INMODE" num_pins="5"/> |
| <input name="OPMODE" num_pins="7"/> |
| <output name="P" num_pins="48"/> |
| <output name="GND_WIRE" num_pins="1"/> |
| <output name="VCC_WIRE" num_pins="1"/> |
| <clock name="CLK" num_pins="1"/> |
| <fc in_type="abs" in_val="1" out_type="abs" out_val="1"/> |
| <pinlocations pattern="spread"/> |
| </tile> |
| <tile name="RAMB36E1" height="5"> |
| <equivalent_sites> |
| <site pb_type="RAMB36E1"/> |
| </equivalent_sites> |
| <input name="ADDRARDADDRL" num_pins="16"/> |
| <input name="ADDRARDADDRU" num_pins="15"/> |
| <input name="ADDRBWRADDRL" num_pins="16"/> |
| <input name="ADDRBWRADDRU" num_pins="15"/> |
| <input name="DIADI" num_pins="32"/> |
| <input name="DIPADIP" num_pins="4"/> |
| <input name="WEAL" num_pins="4"/> |
| <input name="WEAU" num_pins="4"/> |
| <input name="DIBDI" num_pins="32"/> |
| <input name="DIPBDIP" num_pins="4"/> |
| <input name="WEBWEL" num_pins="8"/> |
| <input name="WEBWEU" num_pins="8"/> |
| <input name="ENARDENL" num_pins="1"/> |
| <input name="ENARDENU" num_pins="1"/> |
| <input name="ENBWRENL" num_pins="1"/> |
| <input name="ENBWRENU" num_pins="1"/> |
| <input name="REGCEAREGCEL" num_pins="1"/> |
| <input name="REGCEAREGCEU" num_pins="1"/> |
| <input name="REGCEBL" num_pins="1"/> |
| <input name="REGCEBU" num_pins="1"/> |
| <input name="RSTRAMARSTRAMLRST" num_pins="1"/> |
| <input name="RSTRAMARSTRAMU" num_pins="1"/> |
| <input name="RSTRAMBL" num_pins="1"/> |
| <input name="RSTRAMBU" num_pins="1"/> |
| <input name="RSTREGARSTREGL" num_pins="1"/> |
| <input name="RSTREGARSTREGU" num_pins="1"/> |
| <input name="RSTREGBL" num_pins="1"/> |
| <input name="RSTREGBU" num_pins="1"/> |
| <input name="s0_ADDRARDADDR" num_pins="14"/> |
| <input name="s0_ADDRBWRADDR" num_pins="14"/> |
| <input name="s0_DIADI" num_pins="16"/> |
| <input name="s0_DIPADIP" num_pins="2"/> |
| <input name="s0_WEA" num_pins="4"/> |
| <input name="s0_DIBDI" num_pins="16"/> |
| <input name="s0_DIPBDIP" num_pins="2"/> |
| <input name="s0_WEBWE" num_pins="8"/> |
| <input name="s0_ENARDEN" num_pins="1"/> |
| <input name="s0_ENBWREN" num_pins="1"/> |
| <input name="s0_ADDRATIEHIGH" num_pins="2"/> |
| <input name="s0_ADDRBTIEHIGH" num_pins="2"/> |
| <input name="s0_REGCEAREGCE" num_pins="1"/> |
| <input name="s0_REGCEB" num_pins="1"/> |
| <input name="s0_RSTRAMARSTRAM" num_pins="1"/> |
| <input name="s0_RSTRAMB" num_pins="1"/> |
| <input name="s0_RSTREGARSTREG" num_pins="1"/> |
| <input name="s0_RSTREGB" num_pins="1"/> |
| <input name="s1_ADDRARDADDR" num_pins="14"/> |
| <input name="s1_ADDRBWRADDR" num_pins="14"/> |
| <input name="s1_DIADI" num_pins="16"/> |
| <input name="s1_DIPADIP" num_pins="2"/> |
| <input name="s1_WEA" num_pins="4"/> |
| <input name="s1_DIBDI" num_pins="16"/> |
| <input name="s1_DIPBDIP" num_pins="2"/> |
| <input name="s1_WEBWE" num_pins="8"/> |
| <input name="s1_ENARDEN" num_pins="1"/> |
| <input name="s1_ENBWREN" num_pins="1"/> |
| <input name="s1_ADDRATIEHIGH" num_pins="2"/> |
| <input name="s1_ADDRBTIEHIGH" num_pins="2"/> |
| <input name="s1_REGCEAREGCE" num_pins="1"/> |
| <input name="s1_REGCEB" num_pins="1"/> |
| <input name="s1_RSTRAMARSTRAM" num_pins="1"/> |
| <input name="s1_RSTRAMB" num_pins="1"/> |
| <input name="s1_RSTREGARSTREG" num_pins="1"/> |
| <input name="s1_RSTREGB" num_pins="1"/> |
| <output name="DOADO" num_pins="32"/> |
| <output name="DOPADOP" num_pins="4"/> |
| <output name="DOBDO" num_pins="32"/> |
| <output name="DOPBDOP" num_pins="4"/> |
| <output name="s0_DOADO" num_pins="16"/> |
| <output name="s0_DOPADOP" num_pins="2"/> |
| <output name="s0_DOBDO" num_pins="16"/> |
| <output name="s0_DOPBDOP" num_pins="2"/> |
| <output name="s1_DOADO" num_pins="16"/> |
| <output name="s1_DOPADOP" num_pins="2"/> |
| <output name="s1_DOBDO" num_pins="16"/> |
| <output name="s1_DOPBDOP" num_pins="2"/> |
| <output name="GND_WIRE" num_pins="1"/> |
| <output name="VCC_WIRE" num_pins="1"/> |
| <clock name="CLKARDCLKL" num_pins="1"/> |
| <clock name="CLKARDCLKU" num_pins="1"/> |
| <clock name="CLKBWRCLKL" num_pins="1"/> |
| <clock name="CLKBWRCLKU" num_pins="1"/> |
| <clock name="s0_CLKARDCLK" num_pins="1"/> |
| <clock name="s0_CLKBWRCLK" num_pins="1"/> |
| <clock name="s1_CLKARDCLK" num_pins="1"/> |
| <clock name="s1_CLKBWRCLK" num_pins="1"/> |
| <clock name="REGCLKARDRCLKL" num_pins="1"/> |
| <clock name="REGCLKARDRCLKU" num_pins="1"/> |
| <clock name="REGCLKBL" num_pins="1"/> |
| <clock name="REGCLKBU" num_pins="1"/> |
| <clock name="s0_REGCLKARDRCLK" num_pins="1"/> |
| <clock name="s0_REGCLKB" num_pins="1"/> |
| <clock name="s1_REGCLKARDRCLK" num_pins="1"/> |
| <clock name="s1_REGCLKB" num_pins="1"/> |
| <fc in_type="abs" in_val="1" out_type="abs" out_val="1"/> |
| <pinlocations pattern="spread"/> |
| </tile> |
| <tile name="BUFG" height="2" capacity="16"> |
| <equivalent_sites> |
| <site pb_type="BUFG"/> |
| </equivalent_sites> |
| <input name="I" num_pins="2"/> |
| <input name="S" num_pins="2"/> |
| <input name="CE" num_pins="2"/> |
| <input name="IGNORE" num_pins="2"/> |
| <output name="O" num_pins="1"/> |
| <output name="GND_WIRE" num_pins="1"/> |
| <output name="VCC_WIRE" num_pins="1"/> |
| <fc in_type="abs" in_val="1" out_type="abs" out_val="1"/> |
| <pinlocations pattern="spread"/> |
| </tile> |
| </tiles> |
| <!-- ODIN II specific config ends --> |
| <layout> |
| <fixed_layout name="xc6vlx240tff1156" width="103" height="242"> |
| <perimeter type="EMPTY" priority="30"/> |
| <!-- IOBs --> |
| <col type="IOB" startx="0" starty="1" priority="100"/> |
| <col type="IOB" startx="41" starty="1" priority="100"/> |
| <col type="IOB" startx="57" starty="1" priority="100"/> |
| <!-- Unbonded IOBs --> |
| <col type="EMPTY" startx="0" starty="2" incry="2" priority="400"/> |
| <col type="EMPTY" startx="0" starty="201" priority="500"/> |
| <col type="EMPTY" startx="41" starty="2" incry="2" priority="400"/> |
| <col type="EMPTY" startx="41" starty="201" priority="500"/> |
| <col type="EMPTY" startx="57" starty="2" incry="2" priority="400"/> |
| <col type="EMPTY" startx="57" starty="201" priority="500"/> |
| <!--Fill with 'SLICEL'--> |
| <fill type="SLICEL" priority="10"/> |
| <!-- DSP Columns --> |
| <col type="DSP48E1" startx="8" starty="1" priority="20"/> |
| <col type="DSP48E1" startx="13" starty="1" priority="20"/> |
| <col type="DSP48E1" startx="28" starty="1" priority="20"/> |
| <col type="DSP48E1" startx="33" starty="1" priority="20"/> |
| <col type="DSP48E1" startx="65" starty="1" priority="20"/> |
| <col type="DSP48E1" startx="70" starty="1" priority="20"/> |
| <col type="DSP48E1" startx="85" starty="1" priority="20"/> |
| <col type="DSP48E1" startx="90" starty="1" priority="20"/> |
| <!-- RAM Columns --> |
| <col type="RAMB36E1" startx="5" starty="1" priority="20"/> |
| <col type="RAMB36E1" startx="16" starty="1" priority="20"/> |
| <col type="RAMB36E1" startx="25" starty="1" priority="20"/> |
| <col type="RAMB36E1" startx="36" starty="1" priority="20"/> |
| <col type="RAMB36E1" startx="62" starty="1" priority="20"/> |
| <col type="RAMB36E1" startx="73" starty="1" priority="20"/> |
| <col type="RAMB36E1" startx="82" starty="1" priority="20"/> |
| <col type="RAMB36E1" startx="93" starty="1" priority="20"/> |
| <col type="RAMB36E1" startx="101" starty="1" priority="20"/> |
| <!-- Empty column at 52 (CMT) --> |
| <col type="EMPTY" startx="52" starty="1" priority="19"/> |
| <!-- BUFG --> |
| <region type="BUFG" startx="52" endx="52" starty="119" endy="122" priority="20"/> |
| <!-- Empty region in the middle --> |
| <region type="EMPTY" startx="46" starty="81" endx="51" endy="160" priority="1000"/> |
| <!-- PCIE/EMACs on far right--> |
| <region type="EMPTY" startx="98" starty="41" endx="101" endy="60" priority="1000"/> |
| <region type="EMPTY" startx="101" starty="81" endx="101" endy="100" priority="1000"/> |
| <region type="EMPTY" startx="98" starty="121" endx="101" endy="140" priority="1000"/> |
| <region type="EMPTY" startx="101" starty="161" endx="101" endy="180" priority="1000"/> |
| </fixed_layout> |
| </layout> |
| <device> |
| <sizing R_minW_nmos="0" R_minW_pmos="0"/> |
| <area grid_logic_tile_area="0"/> |
| <chan_width_distr> |
| <x distr="uniform" peak="1.000000"/> |
| <y distr="uniform" peak="1.000000"/> |
| </chan_width_distr> |
| <switch_block type="wilton" fs="3"/> |
| <connection_block input_switch_name="ipin_cblock"/> |
| </device> |
| <switchlist> |
| <switch type="mux" name="default" R="0" Cin="0" Cout="0" Tdel="0" mux_trans_size="1" buf_size="0"/> |
| <switch type="mux" name="L1" R="0" Cin="0" Cout="0" Tdel="0.11e-9" mux_trans_size="1" buf_size="0"/> |
| <switch type="mux" name="L2" R="0" Cin="0" Cout="0" Tdel="0.15e-9" mux_trans_size="1" buf_size="0"/> |
| <switch type="mux" name="L4" R="0" Cin="0" Cout="0" Tdel="0.20e-9" mux_trans_size="1" buf_size="0"/> |
| <!-- No L6 in V6 --> |
| <switch type="mux" name="L6" R="0" Cin="0" Cout="0" Tdel="0" mux_trans_size="1" buf_size="0"/> |
| <!-- No L12 in V6 --> |
| <switch type="mux" name="LH12" R="0" Cin="0" Cout="0" Tdel="0" mux_trans_size="1" buf_size="0"/> |
| <switch type="mux" name="LV12" R="0" Cin="0" Cout="0" Tdel="0" mux_trans_size="1" buf_size="0"/> |
| <switch type="mux" name="L16" R="0" Cin="0" Cout="0" Tdel="0.60e-9" mux_trans_size="1" buf_size="0"/> |
| <!-- No L18 in V6 --> |
| <switch type="mux" name="LV18" R="0" Cin="0" Cout="0" Tdel="0" mux_trans_size="1" buf_size="0"/> |
| <!-- iswitch = 9 --> |
| <switch type="mux" name="A6" R="0" Cin="0" Cout="0" Tdel="0.12e-9" mux_trans_size="1" buf_size="0"/> |
| <switch type="mux" name="A5" R="0" Cin="0" Cout="0" Tdel="0.19e-9" mux_trans_size="1" buf_size="0"/> |
| <switch type="mux" name="A4" R="0" Cin="0" Cout="0" Tdel="0.29e-9" mux_trans_size="1" buf_size="0"/> |
| <switch type="mux" name="A3" R="0" Cin="0" Cout="0" Tdel="0.35e-9" mux_trans_size="1" buf_size="0"/> |
| <switch type="mux" name="A2" R="0" Cin="0" Cout="0" Tdel="0.48e-9" mux_trans_size="1" buf_size="0"/> |
| <switch type="mux" name="A1" R="0" Cin="0" Cout="0" Tdel="0.49e-9" mux_trans_size="1" buf_size="0"/> |
| <switch type="mux" name="LUT" R="0" Cin="0" Cout="0" Tdel="0.068e-9" mux_trans_size="1" buf_size="0"/> |
| <!-- iswitch = 16 --> |
| <switch type="mux" name="BYP" R="0" Cin="0" Cout="0" Tdel="0.11e-9" mux_trans_size="1" buf_size="0"/> |
| <switch type="mux" name="BYP_B" R="0" Cin="0" Cout="0" Tdel="0" mux_trans_size="1" buf_size="0"/> |
| <switch type="mux" name="FAN" R="0" Cin="0" Cout="0" Tdel="0.11e-9" mux_trans_size="1" buf_size="0"/> |
| <!-- iswitch = 19 --> |
| <switch type="mux" name="BRAM_DI" R="0" Cin="0" Cout="0" Tdel="0" mux_trans_size="1" buf_size="0"/> |
| <switch type="mux" name="BRAM_AD" R="0" Cin="0" Cout="0" Tdel="0" mux_trans_size="1" buf_size="0"/> |
| <switch type="mux" name="BRAM_WE" R="0" Cin="0" Cout="0" Tdel="0" mux_trans_size="1" buf_size="0"/> |
| <!-- iswitch = 22 --> |
| <switch type="mux" name="DSP_A" R="0" Cin="0" Cout="0" Tdel="0" mux_trans_size="1" buf_size="0"/> |
| <switch type="mux" name="DSP_B" R="0" Cin="0" Cout="0" Tdel="0" mux_trans_size="1" buf_size="0"/> |
| <!-- iswitch = 24 --> |
| <switch type="mux" name="clk2gen" R="0" Cin="0" Cout="0" Tdel="0" mux_trans_size="1" buf_size="0"/> |
| <switch type="mux" name="gen2clk" R="0" Cin="0" Cout="0" Tdel="0" mux_trans_size="1" buf_size="0"/> |
| <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> |
| <switch type="mux" name="ipin_cblock" R="0.0" Cout="0." Cin="0" Tdel="0" mux_trans_size="0" buf_size="auto"/> |
| </switchlist> |
| <segmentlist> |
| <!-- cost_index = CHANX_COST_INDEX_START = 4 --> |
| <segment freq="1" length="1" type="unidir" Rmetal="0" Cmetal="0"> |
| <mux name="default"/> |
| <sb type="pattern">0 0</sb> |
| <cb type="pattern"> 0 </cb> |
| </segment> |
| <!-- clock cost index --> |
| <segment freq="1" length="1" type="unidir" Rmetal="0" Cmetal="0"> |
| <mux name="default"/> |
| <sb type="pattern">0 0</sb> |
| <cb type="pattern"> 0 </cb> |
| </segment> |
| <!-- cost_index = 6 --> |
| <segment freq="1" length="1" type="unidir" Rmetal="0" Cmetal="0"> |
| <mux name="L1"/> |
| <sb type="pattern">1 1</sb> |
| <cb type="pattern"> 1 </cb> |
| </segment> |
| <segment freq="1" length="2" type="unidir" Rmetal="0" Cmetal="0"> |
| <mux name="L2"/> |
| <sb type="pattern">1 1 1</sb> |
| <cb type="pattern"> 1 1 </cb> |
| </segment> |
| <segment freq="1" length="4" type="unidir" Rmetal="0" Cmetal="0"> |
| <mux name="L4"/> |
| <sb type="pattern">1 1 1 1 1</sb> |
| <cb type="pattern"> 1 1 1 1 </cb> |
| </segment> |
| <!-- No L6, L12 or L16 in V6 --> |
| <segment freq="0" length="6" type="unidir" Rmetal="0" Cmetal="0"> |
| <mux name="L6"/> |
| <sb type="pattern">1 1 1 1 1 1 1</sb> |
| <cb type="pattern"> 1 1 1 1 1 1</cb> |
| </segment> |
| <segment freq="0" length="12" type="unidir" Rmetal="0" Cmetal="0"> |
| <mux name="LH12"/> |
| <sb type="pattern">1 0 0 0 0 0 1 0 0 0 0 0 1</sb> |
| <cb type="pattern"> 1 0 0 0 0 0 0 0 0 0 0 1 </cb> |
| </segment> |
| <segment freq="0" length="12" type="unidir" Rmetal="0" Cmetal="0"> |
| <mux name="LV12"/> |
| <sb type="pattern">1 0 0 0 0 0 0 0 0 0 0 0 1</sb> |
| <cb type="pattern"> 1 0 0 0 0 0 0 0 0 0 0 1 </cb> |
| </segment> |
| <segment freq="1" length="16" type="unidir" Rmetal="0" Cmetal="0"> |
| <mux name="L16"/> |
| <sb type="pattern">1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1</sb> |
| <cb type="pattern"> 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 </cb> |
| </segment> |
| <segment freq="0" length="18" type="unidir" Rmetal="0" Cmetal="0"> |
| <mux name="LV18"/> |
| <sb type="pattern">1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1</sb> |
| <cb type="pattern"> 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 </cb> |
| </segment> |
| </segmentlist> |
| <overrideslist> |
| <!-- Unbonded IOBs --> |
| <region type="EMPTY" startx="0" starty="2" endx="0" endy="200" incy="2"/> |
| <region type="EMPTY" startx="0" starty="201" endx="0" endy="240"/> |
| <region type="EMPTY" startx="41" starty="2" endx="41" endy="200" incy="2"/> |
| <region type="EMPTY" startx="41" starty="201" endx="41" endy="240"/> |
| <region type="EMPTY" startx="57" starty="2" endx="57" endy="200" incy="2"/> |
| <region type="EMPTY" startx="57" starty="201" endx="57" endy="240"/> |
| <!-- IO right edge --> |
| <region type="EMPTY" startx="103" starty="1" endx="103" endy="240"/> |
| <!-- IO top and bottom edge --> |
| <region type="EMPTY" startx="1" starty="0" endx="102" endy="0"/> |
| <region type="EMPTY" startx="1" starty="241" endx="102" endy="241"/> |
| <!-- Empty region in the middle --> |
| <region type="EMPTY" startx="46" starty="81" endx="51" endy="160"/> |
| <!-- PCIE/EMACs on far right--> |
| <region type="EMPTY" startx="98" starty="41" endx="101" endy="60"/> |
| <region type="EMPTY" startx="101" starty="81" endx="101" endy="100"/> |
| <region type="EMPTY" startx="98" starty="121" endx="101" endy="140"/> |
| <region type="EMPTY" startx="101" starty="161" endx="101" endy="180"/> |
| <!-- Empty columns at 52 (CMT) and 102 (GTX) --> |
| <region type="EMPTY" startx="52" starty="1" endx="52" endy="118"/> |
| <region type="EMPTY" startx="52" starty="123" endx="52" endy="240"/> |
| <region type="EMPTY" startx="102" starty="1" endx="102" endy="240"/> |
| </overrideslist> |
| <!-- Used for determining placement macros only? --> |
| <directlist> |
| <direct name="SLICEL_CIN_COUT" from_pin="SLICEL.COUT" to_pin="SLICEL.CIN" x_offset="0" y_offset="1" z_offset="0"/> |
| <!-- Doesn't seem to do anything ... |
| <direct name="SLICE_A1_DIRECT[0]" from_pin="SLICE.CQ" to_pin="SLICE.A6-1 [5:5]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_A1_DIRECT[1]+" from_pin="SLICE.AMUX" to_pin="SLICE.A6-1 [5:5]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_A1_DIRECT[1]-" from_pin="SLICE.AMUX" to_pin="SLICE.A6-1 [5:5]" x_offset="0" y_offset="0" z_offset="-1"/> |
| <direct name="SLICE_A1_DIRECT[2]+" from_pin="SLICE.C" to_pin="SLICE.A6-1 [5:5]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_A1_DIRECT[2]-" from_pin="SLICE.C" to_pin="SLICE.A6-1 [5:5]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_A2_DIRECT[0]" from_pin="SLICE.B" to_pin="SLICE.A6-1 [4:4]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_A2_DIRECT[1]" from_pin="SLICE.DMUX" to_pin="SLICE.A6-1 [4:4]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_A2_DIRECT[2]+" from_pin="SLICE.BQ" to_pin="SLICE.A6-1 [4:4]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_A2_DIRECT[2]-" from_pin="SLICE.BQ" to_pin="SLICE.A6-1 [4:4]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_A3_DIRECT[0]" from_pin="SLICE.AMUX" to_pin="SLICE.A6-1 [3:3]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_A3_DIRECT[1]" from_pin="SLICE.C" to_pin="SLICE.A6-1 [3:3]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_A3_DIRECT[2]+" from_pin="SLICE.CQ" to_pin="SLICE.A6-1 [3:3]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_A3_DIRECT[2]-" from_pin="SLICE.CQ" to_pin="SLICE.A6-1 [3:3]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_A4_DIRECT[0]" from_pin="SLICE.DQ" to_pin="SLICE.A6-1 [2:2]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_A4_DIRECT[1]+" from_pin="SLICE.BMUX" to_pin="SLICE.A6-1 [2:2]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_A4_DIRECT[1]-" from_pin="SLICE.BMUX" to_pin="SLICE.A6-1 [2:2]" x_offset="0" y_offset="0" z_offset="-1"/> |
| <direct name="SLICE_A4_DIRECT[2]+" from_pin="SLICE.D" to_pin="SLICE.A6-1 [2:2]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_A4_DIRECT[2]-" from_pin="SLICE.D" to_pin="SLICE.A6-1 [2:2]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_A5_DIRECT[0]" from_pin="SLICE.AQ" to_pin="SLICE.A6-1 [1:1]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_A5_DIRECT[1]+" from_pin="SLICE.A" to_pin="SLICE.A6-1 [1:1]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_A5_DIRECT[1]-" from_pin="SLICE.A" to_pin="SLICE.A6-1 [1:1]" x_offset="0" y_offset="0" z_offset="-1"/> |
| <direct name="SLICE_A5_DIRECT[2]+" from_pin="SLICE.CMUX" to_pin="SLICE.A6-1 [1:1]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_A5_DIRECT[2]-" from_pin="SLICE.CMUX" to_pin="SLICE.A6-1 [1:1]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_A6_DIRECT[0]" from_pin="SLICE.B" to_pin="SLICE.A6-1 [0:0]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_A6_DIRECT[1]" from_pin="SLICE.DMUX" to_pin="SLICE.A6-1 [0:0]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_A6_DIRECT[2]+" from_pin="SLICE.BQ" to_pin="SLICE.A6-1 [0:0]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_A6_DIRECT[2]-" from_pin="SLICE.BQ" to_pin="SLICE.A6-1 [0:0]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_B1_DIRECT[0]" from_pin="SLICE.AQ" to_pin="SLICE.B6-1 [5:5]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_B1_DIRECT[1]+" from_pin="SLICE.A" to_pin="SLICE.B6-1 [5:5]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_B1_DIRECT[1]-" from_pin="SLICE.A" to_pin="SLICE.B6-1 [5:5]" x_offset="0" y_offset="0" z_offset="-1"/> |
| <direct name="SLICE_B1_DIRECT[2]+" from_pin="SLICE.CMUX" to_pin="SLICE.B6-1 [5:5]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_B1_DIRECT[2]-" from_pin="SLICE.CMUX" to_pin="SLICE.B6-1 [5:5]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_B2_DIRECT[0]" from_pin="SLICE.BMUX" to_pin="SLICE.B6-1 [4:4]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_B2_DIRECT[1]+" from_pin="SLICE.D" to_pin="SLICE.B6-1 [4:4]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_B2_DIRECT[2]+" from_pin="SLICE.DQ" to_pin="SLICE.B6-1 [4:4]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_B2_DIRECT[2]-" from_pin="SLICE.DQ" to_pin="SLICE.B6-1 [4:4]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_B3_DIRECT[0]" from_pin="SLICE.A" to_pin="SLICE.B6-1 [3:3]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_B3_DIRECT[1]+" from_pin="SLICE.CMUX" to_pin="SLICE.B6-1 [3:3]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_B3_DIRECT[2]+" from_pin="SLICE.AQ" to_pin="SLICE.B6-1 [3:3]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_B3_DIRECT[2]-" from_pin="SLICE.AQ" to_pin="SLICE.B6-1 [3:3]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_B4_DIRECT[0]" from_pin="SLICE.BQ" to_pin="SLICE.B6-1 [2:2]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_B4_DIRECT[1]+" from_pin="SLICE.B" to_pin="SLICE.B6-1 [2:2]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_B4_DIRECT[1]-" from_pin="SLICE.B" to_pin="SLICE.B6-1 [2:2]" x_offset="0" y_offset="0" z_offset="-1"/> |
| <direct name="SLICE_B4_DIRECT[2]+" from_pin="SLICE.DMUX" to_pin="SLICE.B6-1 [2:2]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_B4_DIRECT[2]-" from_pin="SLICE.DMUX" to_pin="SLICE.B6-1 [2:2]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_B5_DIRECT[0]" from_pin="SLICE.CQ" to_pin="SLICE.B6-1 [1:1]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_B5_DIRECT[1]+" from_pin="SLICE.AMUX" to_pin="SLICE.B6-1 [1:1]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_B5_DIRECT[1]-" from_pin="SLICE.AMUX" to_pin="SLICE.B6-1 [1:1]" x_offset="0" y_offset="0" z_offset="-1"/> |
| <direct name="SLICE_B5_DIRECT[2]+" from_pin="SLICE.C" to_pin="SLICE.B6-1 [1:1]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_B5_DIRECT[2]-" from_pin="SLICE.C" to_pin="SLICE.B6-1 [1:1]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_B6_DIRECT[0]" from_pin="SLICE.BMUX" to_pin="SLICE.B6-1 [0:0]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_B6_DIRECT[1]+" from_pin="SLICE.B" to_pin="SLICE.A6-1 [0:0]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_B6_DIRECT[2]+" from_pin="SLICE.DQ" to_pin="SLICE.A6-1 [0:0]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_B6_DIRECT[2]-" from_pin="SLICE.DQ" to_pin="SLICE.A6-1 [0:0]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_C1_DIRECT[0]" from_pin="SLICE.AQ" to_pin="SLICE.C6-1 [5:5]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_C1_DIRECT[1]+" from_pin="SLICE.A" to_pin="SLICE.C6-1 [5:5]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_C1_DIRECT[1]-" from_pin="SLICE.A" to_pin="SLICE.C6-1 [5:5]" x_offset="0" y_offset="0" z_offset="-1"/> |
| <direct name="SLICE_C1_DIRECT[2]+" from_pin="SLICE.CMUX" to_pin="SLICE.C6-1 [5:5]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_C1_DIRECT[2]-" from_pin="SLICE.CMUX" to_pin="SLICE.C6-1 [5:5]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_C2_DIRECT[0]" from_pin="SLICE.BMUX" to_pin="SLICE.C6-1 [4:4]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_C2_DIRECT[1]+" from_pin="SLICE.D" to_pin="SLICE.C6-1 [4:4]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_C2_DIRECT[2]+" from_pin="SLICE.DQ" to_pin="SLICE.C6-1 [4:4]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_C2_DIRECT[2]-" from_pin="SLICE.DQ" to_pin="SLICE.C6-1 [4:4]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_C3_DIRECT[0]" from_pin="SLICE.A" to_pin="SLICE.C6-1 [3:3]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_C3_DIRECT[1]+" from_pin="SLICE.CMUX" to_pin="SLICE.C6-1 [3:3]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_C3_DIRECT[2]+" from_pin="SLICE.AQ" to_pin="SLICE.C6-1 [3:3]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_C3_DIRECT[2]-" from_pin="SLICE.AQ" to_pin="SLICE.C6-1 [3:3]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_C4_DIRECT[0]" from_pin="SLICE.BQ" to_pin="SLICE.C6-1 [2:2]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_C4_DIRECT[1]+" from_pin="SLICE.B" to_pin="SLICE.C6-1 [2:2]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_C4_DIRECT[1]-" from_pin="SLICE.B" to_pin="SLICE.C6-1 [2:2]" x_offset="0" y_offset="0" z_offset="-1"/> |
| <direct name="SLICE_C4_DIRECT[2]+" from_pin="SLICE.DMUX" to_pin="SLICE.C6-1 [2:2]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_C4_DIRECT[2]-" from_pin="SLICE.DMUX" to_pin="SLICE.C6-1 [2:2]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_C5_DIRECT[0]" from_pin="SLICE.CQ" to_pin="SLICE.C6-1 [1:1]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_C5_DIRECT[1]+" from_pin="SLICE.AMUX" to_pin="SLICE.C6-1 [1:1]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_C5_DIRECT[1]-" from_pin="SLICE.AMUX" to_pin="SLICE.C6-1 [1:1]" x_offset="0" y_offset="0" z_offset="-1"/> |
| <direct name="SLICE_C5_DIRECT[2]+" from_pin="SLICE.C" to_pin="SLICE.C6-1 [1:1]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_C5_DIRECT[2]-" from_pin="SLICE.C" to_pin="SLICE.C6-1 [1:1]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_C6_DIRECT[0]" from_pin="SLICE.BMUX" to_pin="SLICE.C6-1 [0:0]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_C6_DIRECT[1]" from_pin="SLICE.D" to_pin="SLICE.C6-1 [0:0]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_C6_DIRECT[2]+" from_pin="SLICE.DQ" to_pin="SLICE.C6-1 [0:0]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_C6_DIRECT[2]-" from_pin="SLICE.DQ" to_pin="SLICE.C6-1 [0:0]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_D1_DIRECT[0]" from_pin="SLICE.CQ" to_pin="SLICE.D6-1 [5:5]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_D1_DIRECT[1]+" from_pin="SLICE.AMUX" to_pin="SLICE.D6-1 [5:5]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_D1_DIRECT[1]-" from_pin="SLICE.AMUX" to_pin="SLICE.D6-1 [5:5]" x_offset="0" y_offset="0" z_offset="-1"/> |
| <direct name="SLICE_D1_DIRECT[2]+" from_pin="SLICE.C" to_pin="SLICE.D6-1 [5:5]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_D1_DIRECT[2]-" from_pin="SLICE.C" to_pin="SLICE.D6-1 [5:5]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_D2_DIRECT[0]" from_pin="SLICE.B" to_pin="SLICE.D6-1 [4:4]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_D2_DIRECT[1]" from_pin="SLICE.DMUX" to_pin="SLICE.D6-1 [4:4]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_D2_DIRECT[2]+" from_pin="SLICE.BQ" to_pin="SLICE.D6-1 [4:4]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_D2_DIRECT[2]-" from_pin="SLICE.BQ" to_pin="SLICE.D6-1 [4:4]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_D3_DIRECT[0]" from_pin="SLICE.A" to_pin="SLICE.D6-1 [3:3]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_D3_DIRECT[1]" from_pin="SLICE.AMUX" to_pin="SLICE.D6-1 [3:3]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_D3_DIRECT[2]+" from_pin="SLICE.CQ" to_pin="SLICE.D6-1 [3:3]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_D3_DIRECT[2]-" from_pin="SLICE.CQ" to_pin="SLICE.D6-1 [3:3]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_D4_DIRECT[0]" from_pin="SLICE.DQ" to_pin="SLICE.D6-1 [2:2]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_D4_DIRECT[1]+" from_pin="SLICE.BMUX" to_pin="SLICE.D6-1 [2:2]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_D4_DIRECT[1]-" from_pin="SLICE.BMUX" to_pin="SLICE.D6-1 [2:2]" x_offset="0" y_offset="0" z_offset="-1"/> |
| <direct name="SLICE_D4_DIRECT[2]+" from_pin="SLICE.D" to_pin="SLICE.D6-1 [2:2]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_D4_DIRECT[2]-" from_pin="SLICE.D" to_pin="SLICE.D6-1 [2:2]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_D5_DIRECT[0]" from_pin="SLICE.AQ" to_pin="SLICE.D6-1 [1:1]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_D5_DIRECT[1]+" from_pin="SLICE.A" to_pin="SLICE.D6-1 [1:1]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_D5_DIRECT[1]-" from_pin="SLICE.A" to_pin="SLICE.D6-1 [1:1]" x_offset="0" y_offset="0" z_offset="-1"/> |
| <direct name="SLICE_D5_DIRECT[2]+" from_pin="SLICE.CMUX" to_pin="SLICE.D6-1 [1:1]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_D5_DIRECT[2]-" from_pin="SLICE.CMUX" to_pin="SLICE.D6-1 [1:1]" x_offset="0" y_offset="0" z_offset="-1"/> |
| |
| <direct name="SLICE_D6_DIRECT[0]" from_pin="SLICE.B" to_pin="SLICE.D6-1 [0:0]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_D6_DIRECT[1]" from_pin="SLICE.DMUX" to_pin="SLICE.D6-1 [0:0]" x_offset="0" y_offset="0" z_offset="0" /> |
| <direct name="SLICE_D6_DIRECT[2]+" from_pin="SLICE.BQ" to_pin="SLICE.D6-1 [0:0]" x_offset="0" y_offset="0" z_offset="1" /> |
| <direct name="SLICE_D6_DIRECT[2]-" from_pin="SLICE.BQ" to_pin="SLICE.D6-1 [0:0]" x_offset="0" y_offset="0" z_offset="-1"/> |
| --> |
| </directlist> |
| <complexblocklist> |
| <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> |
| <!-- TODO: Support IOB registers --> |
| <pb_type name="IOB"> |
| <!-- 0 and 4 --> |
| <input name="O" num_pins="1"/> |
| <!-- 1 and 5 --> |
| <output name="I" num_pins="1"/> |
| <!-- 2 and 6 --> |
| <output name="GND_WIRE" num_pins="1"/> |
| <!-- 3 and 7 --> |
| <output name="VCC_WIRE" num_pins="1"/> |
| <!-- IOs can operate as either inputs or outputs --> |
| <mode name="ibuf"> |
| <pb_type name="ibuf" blif_model=".input" num_pb="1"> |
| <output name="inpad" num_pins="1"/> |
| </pb_type> |
| <interconnect> |
| <direct name="inpad" input="ibuf.inpad" output="IOB.I"> |
| <!-- TRCE: Tiopi LVCMOS25 --> |
| <delay_constant max="0.846e-9" in_port="ibuf.inpad" out_port="IOB.I"/> |
| </direct> |
| </interconnect> |
| </mode> |
| <mode name="obuf"> |
| <pb_type name="obuf" blif_model=".output" num_pb="1"> |
| <input name="outpad" num_pins="1"/> |
| </pb_type> |
| <interconnect> |
| <direct name="outpad" input="IOB.O" output="obuf.outpad"> |
| <!-- TRCE: Tioop LVCMOS25 --> |
| <delay_constant max="2.349e-9" in_port="IOB.O" out_port="obuf.outpad"/> |
| </direct> |
| </interconnect> |
| </mode> |
| </pb_type> |
| <!-- TODO: Support F7/F8MUX --> |
| <pb_type name="SLICEL"> |
| <!-- 0 / 95: --> |
| <input name="A6-1" num_pins="6" equivalent="full"/> |
| <input name="A6_VCCONLY" num_pins="1" equivalent="none"/> |
| <input name="AX" num_pins="1" equivalent="none"/> |
| <input name="B6-1" num_pins="6" equivalent="full"/> |
| <input name="B6_VCCONLY" num_pins="1" equivalent="none"/> |
| <input name="BX" num_pins="1" equivalent="none"/> |
| <input name="C6-1" num_pins="6" equivalent="full"/> |
| <input name="C6_VCCONLY" num_pins="1" equivalent="none"/> |
| <input name="CX" num_pins="1" equivalent="none"/> |
| <input name="D6-1" num_pins="6" equivalent="full"/> |
| <input name="D6_VCCONLY" num_pins="1" equivalent="none"/> |
| <input name="DX" num_pins="1" equivalent="none"/> |
| <!-- 32 / 81: --> |
| <input name="CIN" num_pins="1" equivalent="none"/> |
| <!-- 33 / 73: --> |
| <output name="A" num_pins="1" equivalent="none"/> |
| <output name="AQ" num_pins="1" equivalent="none"/> |
| <output name="AMUX" num_pins="1" equivalent="none"/> |
| <output name="B" num_pins="1" equivalent="none"/> |
| <output name="BQ" num_pins="1" equivalent="none"/> |
| <output name="BMUX" num_pins="1" equivalent="none"/> |
| <output name="C" num_pins="1" equivalent="none"/> |
| <output name="CQ" num_pins="1" equivalent="none"/> |
| <output name="CMUX" num_pins="1" equivalent="none"/> |
| <output name="D" num_pins="1" equivalent="none"/> |
| <output name="DQ" num_pins="1" equivalent="none"/> |
| <output name="DMUX" num_pins="1" equivalent="none"/> |
| <!-- 45 / 94: --> |
| <output name="COUT" num_pins="1" equivalent="none"/> |
| <!-- 46 / 95: --> |
| <output name="GND_WIRE" num_pins="1"/> |
| <output name="VCC_WIRE" num_pins="1"/> |
| <!-- 48 / 97: --> |
| <clock name="CLK" num_pins="1"/> |
| <mode name="LUT6x4"> |
| <pb_type name="ble6" num_pb="4"> |
| <input name="A6-1" num_pins="6"/> |
| <input name="AX" num_pins="1"/> |
| <input name="CIN" num_pins="1"/> |
| <output name="A" num_pins="1"/> |
| <output name="AQ" num_pins="1"/> |
| <output name="AMUX" num_pins="1"/> |
| <output name="COUT" num_pins="1"/> |
| <clock name="CLK" num_pins="1"/> |
| <mode name="O6O5LUT"> |
| <pb_type name="LUT5" blif_model=".names" num_pb="2" class="lut"> |
| <input name="in" num_pins="5" port_class="lut_in"/> |
| <output name="out" num_pins="1" port_class="lut_out"/> |
| <!-- TRCE: Tilo --> |
| <delay_matrix type="max" in_port="LUT5.in" out_port="LUT5.out"> |
| 0.068e-9 |
| 0.068e-9 |
| 0.068e-9 |
| 0.068e-9 |
| 0.068e-9 |
| </delay_matrix> |
| </pb_type> |
| <pb_type name="FF" blif_model=".latch" num_pb="2" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <!-- TRCE: Tas --> |
| <T_setup value="0.301e-9" port="FF.D" clock="clk"/> |
| <!-- TRCE: Tcko --> |
| <T_clock_to_Q max="0.381e-9" port="FF.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="A6-1[0]" input="ble6.A6-1[5:1]" output="LUT5[0].in[4:0]"/> |
| <direct name="A6-1[1]" input="ble6.A6-1[5:1]" output="LUT5[1].in[4:0]"/> |
| <direct name="A" input="LUT5[0].out" output="ble6.A"/> |
| <direct name="AQ" input="FF[0].Q" output="ble6.AQ"/> |
| <mux name="AMUX" input="FF[1].Q LUT5[1].out" output="ble6.AMUX"> |
| <!-- TRCE: Tshcko = 0.468ns - Tcko = 0.381ns --> |
| <delay_constant max="0.087e-9" in_port="FF[1].Q" out_port="ble6.AMUX"/> |
| <!-- TRCE: Tilo (BMUX) = 0.205ns - Tilo = 0.068ns --> |
| <!--delay_constant max="0.137e-9" in_port="LUT5[0].out" out_port="ble6.AMUX"/--> |
| <delay_constant max="0.137e-9" in_port="LUT5[1].out" out_port="ble6.AMUX"/> |
| </mux> |
| <mux name="FF[0].D" input="LUT5[0].out LUT5[1].out ble6.AX" output="FF[0].D"> |
| <pack_pattern name="LUT5-FF" in_port="LUT5[0].out" out_port="FF[0].D"/> |
| <!-- TODO: --> |
| <delay_constant max="0.0e-9" in_port="ble6.AX" out_port="FF[0].D"/> |
| </mux> |
| <mux name="FF[1].D" input="LUT5[1].out ble6.AX" output="FF[1].D"> |
| <pack_pattern name="LUT5-FF" in_port="LUT5[1].out" out_port="FF[1].D"/> |
| </mux> |
| <complete name="clk" input="ble6.CLK" output="FF.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="O6O5LUT_XADDER"> |
| <pb_type name="LUT5" blif_model=".names" num_pb="2" class="lut"> |
| <input name="in" num_pins="5" port_class="lut_in"/> |
| <output name="out" num_pins="1" port_class="lut_out"/> |
| <!-- TRCE: Tilo --> |
| <delay_matrix type="max" in_port="LUT5.in" out_port="LUT5.out"> |
| 0.068e-9 |
| 0.068e-9 |
| 0.068e-9 |
| 0.068e-9 |
| 0.068e-9 |
| </delay_matrix> |
| </pb_type> |
| <pb_type name="XADDER" blif_model=".subckt xadder" num_pb="1"> |
| <input name="a_xor_b" num_pins="1"/> |
| <input name="a_and_b" num_pins="1"/> |
| <input name="cin" num_pins="1"/> |
| <output name="sumout" num_pins="1"/> |
| <output name="cout" num_pins="1"/> |
| <!-- TRCE: Topaa (Ax - AMUX) = 0.329 - Tilo --> |
| <delay_constant max="0.261e-9" in_port="XADDER.a_xor_b" out_port="XADDER.sumout"/> |
| <delay_constant max="0.261e-9" in_port="XADDER.a_and_b" out_port="XADDER.sumout"/> |
| <!-- TRCE: Tcina (CIN - AMUX) --> |
| <delay_constant max="0.248e-9" in_port="XADDER.cin" out_port="XADDER.sumout"/> |
| <!-- TRCE: Topcyd (Dx - COUT) = 0.319 - Tilo --> |
| <delay_constant max="0.251e-9" in_port="XADDER.a_xor_b" out_port="XADDER.cout"/> |
| <delay_constant max="0.251e-9" in_port="XADDER.a_and_b" out_port="XADDER.cout"/> |
| <!-- TRCE: Tbyp = 0.078 / 4 --> |
| <delay_constant max="0.020e-9" in_port="XADDER.cin" out_port="XADDER.cout"/> |
| </pb_type> |
| <pb_type name="FF" blif_model=".latch" num_pb="2" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <!-- TRCE: Tas --> |
| <T_setup value="0.301e-9" port="FF.D" clock="clk"/> |
| <!-- TRCE: Tcko --> |
| <T_clock_to_Q max="0.381e-9" port="FF.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="A6-1[0]" input="ble6.A6-1[5:1]" output="LUT5[0].in[4:0]"/> |
| <direct name="A6-1[1]" input="ble6.A6-1[5:1]" output="LUT5[1].in[4:0]"/> |
| <direct name="A" input="LUT5[0].out" output="ble6.A"/> |
| <direct name="AQ" input="FF[0].Q" output="ble6.AQ"/> |
| <direct name="CIN" input="ble6.CIN" output="XADDER.cin"> |
| <pack_pattern name="SLICEL_carry" in_port="ble6.CIN" out_port="XADDER.cin"/> |
| </direct> |
| <direct name="COUT" input="XADDER.cout" output="ble6.COUT"> |
| <pack_pattern name="SLICEL_carry" in_port="XADDER.cout" out_port="ble6.COUT"/> |
| </direct> |
| <direct name="XADDER_a" input="LUT5[0].out" output="XADDER.a_xor_b"> |
| <pack_pattern name="SLICEL_carry" in_port="LUT5[0].out" out_port="XADDER.a_xor_b"/> |
| </direct> |
| <mux name="XADDER_b" input="LUT5[1].out ble6.AX" output="XADDER.a_and_b"> |
| <!-- TODO: this pattern doesn't work, either in combination with one above, |
| or by itself; pre-pack works, but clustering fails to allow molecule |
| to be implemented .... --> |
| <!--pack_pattern name="SLICEL_carry" in_port="LUT5[1].out" out_port="XADDER.a_and_b"/--> |
| <!-- TODO: TRCE: Taxcy=0.295ns - Topcya=0.410ns --> |
| <delay_constant max="0.0e-9" in_port="ble6.AX" out_port="XADDER.a_and_b"/> |
| </mux> |
| <!-- Do not allow XADDER.cout to go out on AMUX, because sometimes the packer |
| will take this route (instead of COUT) and break the carry chain --> |
| <mux name="AMUX" input="XADDER.sumout" output="ble6.AMUX"/> |
| <!-- |
| TODO: Adding this creates a lot of "Routing failed. Disconnected rr_graph." |
| messages during packing (but ultimately still works)!?! |
| <mux name="FF[0].D" input="XADDER.sumout" output="FF[0].D"> |
| <pack_pattern name="SLICEL_carry" in_port="XADDER.sumout" out_port="FF[0].D"/> |
| <!- -pack_pattern name="SLICEL_carry" in_port="XADDER.cout" out_port="FF[0].D"/- -> |
| <!- - TODO: - -> |
| <delay_constant max="0.0e-9" in_port="ble6.AX" out_port="FF[0].D"/> |
| </mux> |
| --> |
| <!--mux name="FF[1].D" input="LUT5[1].out ble6.AX" output="FF[1].D"> |
| <pack_pattern name="LUT5-FF" in_port="LUT5[1].out" out_port="FF[1].D"/> |
| </mux--> |
| <complete name="clk" input="ble6.CLK" output="FF.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="O6LUT"> |
| <pb_type name="LUT6" blif_model=".names" num_pb="1" class="lut"> |
| <input name="in" num_pins="6" port_class="lut_in"/> |
| <output name="out" num_pins="1" port_class="lut_out"/> |
| <delay_matrix type="max" in_port="LUT6.in" out_port="LUT6.out"> |
| 0.068e-9 |
| 0.068e-9 |
| 0.068e-9 |
| 0.068e-9 |
| 0.068e-9 |
| 0.068e-9 |
| </delay_matrix> |
| </pb_type> |
| <pb_type name="FF" blif_model=".latch" num_pb="2" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <!-- TRCE: Tas --> |
| <T_setup value="0.301e-9" port="FF.D" clock="clk"/> |
| <!-- TRCE: Tcko --> |
| <T_clock_to_Q max="0.381e-9" port="FF.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="A6-1" input="ble6.A6-1[5:0]" output="LUT6.in[5:0]"/> |
| <direct name="A" input="LUT6.out" output="ble6.A"/> |
| <direct name="AQ" input="FF[0].Q" output="ble6.AQ"/> |
| <mux name="AMUX" input="FF[1].Q" output="ble6.AMUX"> |
| <delay_constant max="0.087e-9" in_port="FF[1].Q" out_port="ble6.AMUX"/> |
| <delay_constant max="0.137e-9" in_port="LUT6.out" out_port="ble6.AMUX"/> |
| </mux> |
| <mux name="FF[0].D" input="LUT6.out ble6.AX" output="FF[0].D"> |
| <pack_pattern name="LUT6-FF" in_port="LUT6.out" out_port="FF[0].D"/> |
| <delay_constant max="0.0e-9" in_port="ble6.AX" out_port="FF[0].D"/> |
| </mux> |
| <mux name="FF[1].D" input="ble6.AX" output="FF[1].D"> |
| <delay_constant max="0.0e-9" in_port="ble6.AX" out_port="FF[1].D"/> |
| </mux> |
| <complete name="clk" input="ble6.CLK" output="FF.clk"/> |
| </interconnect> |
| </mode> |
| </pb_type> |
| <pb_type name="DUMMY" blif_model=".subckt adder" num_pb="1"> |
| <input name="a" num_pins="1"/> |
| <input name="b" num_pins="1"/> |
| <input name="cin" num_pins="1"/> |
| <output name="sumout" num_pins="1"/> |
| <output name="cout" num_pins="1"/> |
| </pb_type> |
| <interconnect> |
| <direct name="A6-1" input="SLICEL.A6-1" output="ble6[0].A6-1"/> |
| <direct name="AX" input="SLICEL.AX" output="ble6[0].AX"/> |
| <direct name="A" input="ble6[0].A" output="SLICEL.A"/> |
| <direct name="AQ" input="ble6[0].AQ" output="SLICEL.AQ"/> |
| <direct name="AMUX" input="ble6[0].AMUX" output="SLICEL.AMUX"/> |
| <direct name="B6-1" input="SLICEL.B6-1" output="ble6[1].A6-1"/> |
| <direct name="BX" input="SLICEL.BX" output="ble6[1].AX"/> |
| <direct name="B" input="ble6[1].A" output="SLICEL.B"/> |
| <direct name="BQ" input="ble6[1].AQ" output="SLICEL.BQ"/> |
| <direct name="BMUX" input="ble6[1].AMUX" output="SLICEL.BMUX"/> |
| <direct name="C6-1" input="SLICEL.C6-1" output="ble6[2].A6-1"/> |
| <direct name="CX" input="SLICEL.CX" output="ble6[2].AX"/> |
| <direct name="C" input="ble6[2].A" output="SLICEL.C"/> |
| <direct name="CQ" input="ble6[2].AQ" output="SLICEL.CQ"/> |
| <direct name="CMUX" input="ble6[2].AMUX" output="SLICEL.CMUX"/> |
| <direct name="D6-1" input="SLICEL.D6-1" output="ble6[3].A6-1"/> |
| <direct name="DX" input="SLICEL.DX" output="ble6[3].AX"/> |
| <direct name="D" input="ble6[3].A" output="SLICEL.D"/> |
| <direct name="DQ" input="ble6[3].AQ" output="SLICEL.DQ"/> |
| <direct name="DMUX" input="ble6[3].AMUX" output="SLICEL.DMUX"/> |
| <!--direct name="const0" input="const0.out" output="SLICEL.GND_WIRE"/> |
| <direct name="const1" input="const1.out" output="SLICEL.VCC_WIRE"/--> |
| <direct name="COUT" input="ble6[3].COUT" output="SLICEL.COUT"> |
| <pack_pattern name="SLICEL_carry" in_port="ble6[3].COUT" out_port="SLICEL.COUT"/> |
| </direct> |
| <direct name="chain" input="ble6[2:0].COUT" output="ble6[3:1].CIN"> |
| <pack_pattern name="SLICEL_carry" in_port="ble6[2:0].COUT" out_port="ble6[3:1].CIN"/> |
| </direct> |
| <!-- CIN can be sourced from dedicated CIN pin or from AX port --> |
| <!-- FIXME: But enabling it exposes a bug in the packer: sometimes it chooses |
| to go from COUT -> AX, even though COUT is marked as having no |
| access to the general routing... --> |
| <!--mux name="CIN" input="SLICEL.AX SLICEL.CIN" output="ble6[0].CIN"--> |
| <mux name="CIN" input="SLICEL.CIN" output="ble6[0].CIN"> |
| <pack_pattern name="SLICEL_carry" in_port="SLICEL.CIN" out_port="ble6[0].CIN"/> |
| <!--delay_constant max="0.28e-9" in_port="SLICEL.CIN" out_port="ble6[0].CIN"/--> |
| </mux> |
| <complete name="CLK" input="SLICEL.CLK" output="ble6[3:0].CLK"/> |
| </interconnect> |
| </mode> |
| </pb_type> |
| <pb_type name="DSP48E1"> |
| <!-- 0: --> |
| <input name="A" num_pins="30"/> |
| <!-- 30: --> |
| <input name="B" num_pins="18"/> |
| <!-- 48: --> |
| <input name="CEA1" num_pins="1"/> |
| <input name="CEA2" num_pins="1"/> |
| <input name="CEB1" num_pins="1"/> |
| <input name="CEB2" num_pins="1"/> |
| <input name="CEM" num_pins="1"/> |
| <input name="CEP" num_pins="1"/> |
| <input name="INMODE" num_pins="5"/> |
| <input name="OPMODE" num_pins="7"/> |
| <!-- 66: --> |
| <output name="P" num_pins="48"/> |
| <!-- 114: --> |
| <output name="GND_WIRE" num_pins="1"/> |
| <output name="VCC_WIRE" num_pins="1"/> |
| <!-- 116: --> |
| <clock name="CLK" num_pins="1"/> |
| <!-- Cannot do bussy muxes, so use modes instead --> |
| <!--mode name="mult_25x18_REGABP"> |
| <pb_type name="mult_25x18" blif_model=".subckt multiply" num_pb="1"> |
| <input name="a" num_pins="25" /> |
| <input name="b" num_pins="18" /> |
| <output name="p" num_pins="43"/> |
| <!- - TRCE: T_dspdo_a_p_mult - -> |
| <delay_constant max="3.826e-9" in_port="mult_25x18.a" out_port="mult_25x18.p"/> |
| <!- - TRCE: T_dspdo_b_p_mult - -> |
| <delay_constant max="3.597e-9" in_port="mult_25x18.b" out_port="mult_25x18.p"/> |
| </pb_type> |
| <pb_type name="AREG" blif_model=".latch" num_pb="25" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D" /> |
| <output name="Q" num_pins="1" port_class="Q" /> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <!- - T_dspdck_a_areg - -> |
| <T_setup value="0.24e-9" port="AREG.D" clock="clk"/> |
| </pb_type> |
| <pb_type name="BREG" blif_model=".latch" num_pb="18" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D" /> |
| <output name="Q" num_pins="1" port_class="Q" /> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <!- - T_dspdck_b_breg - -> |
| <T_setup value="0.28e-9" port="BREG.D" clock="clk"/> |
| </pb_type> |
| <pb_type name="PREG" blif_model=".latch" num_pb="43" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D" /> |
| <output name="Q" num_pins="1" port_class="Q" /> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <!- - T_dspcko_p_preg - -> |
| <T_clock_to_Q max="0.33e-9" port="PREG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="AREG" input="DSP48E1.A[24:0]" output="AREG.D" /> |
| <direct name="A" input="AREG.Q" output="mult_25x18.a" /> |
| <direct name="BREG" input="DSP48E1.B[17:0]" output="BREG.D" /> |
| <direct name="B" input="BREG.Q" output="mult_25x18.b" > |
| <!- - FIXME: These patterns do form molecules, but VPR packer |
| overlooks this as a find suitable site - -> |
| <!- -pack_pattern name="DSP-BREG" in_port="BREG[17:0].Q" out_port="mult_25x18.b"/- -> |
| </direct> |
| <direct name="PREG" input="mult_25x18.p" output="PREG.D" > |
| <!- - FIXME: In rare cases (e.g. bgm), some of the multiplier's outputs |
| will be registered, whilst others are not, this causes the pre-packer |
| to pack the subset that is registered into a molecule (e.g. p[17:0]) |
| whilst leaving the unregistered pputs (e.g. p[25:18]) alone causing |
| an unpack-able situation - -> |
| <!- - Enumerate all widths as pack patterns - -> |
| <!- -pack_pattern name="DSP_P[42:0]-PREG" in_port="mult_25x18.p[42:0]" out_port="PREG[42:0].D"/> |
| <pack_pattern name="DSP_P[41:0]-PREG" in_port="mult_25x18.p[41:0]" out_port="PREG[41:0].D"/> |
| <pack_pattern name="DSP_P[40:0]-PREG" in_port="mult_25x18.p[40:0]" out_port="PREG[40:0].D"/> |
| <pack_pattern name="DSP_P[39:0]-PREG" in_port="mult_25x18.p[39:0]" out_port="PREG[39:0].D"/> |
| <pack_pattern name="DSP_P[38:0]-PREG" in_port="mult_25x18.p[38:0]" out_port="PREG[38:0].D"/> |
| <pack_pattern name="DSP_P[37:0]-PREG" in_port="mult_25x18.p[37:0]" out_port="PREG[37:0].D"/> |
| <pack_pattern name="DSP_P[36:0]-PREG" in_port="mult_25x18.p[36:0]" out_port="PREG[36:0].D"/> |
| <pack_pattern name="DSP_P[35:0]-PREG" in_port="mult_25x18.p[35:0]" out_port="PREG[35:0].D"/> |
| <pack_pattern name="DSP_P[34:0]-PREG" in_port="mult_25x18.p[34:0]" out_port="PREG[34:0].D"/> |
| <pack_pattern name="DSP_P[33:0]-PREG" in_port="mult_25x18.p[33:0]" out_port="PREG[33:0].D"/> |
| <pack_pattern name="DSP_P[32:0]-PREG" in_port="mult_25x18.p[32:0]" out_port="PREG[32:0].D"/> |
| <pack_pattern name="DSP_P[31:0]-PREG" in_port="mult_25x18.p[31:0]" out_port="PREG[31:0].D"/> |
| <pack_pattern name="DSP_P[30:0]-PREG" in_port="mult_25x18.p[30:0]" out_port="PREG[30:0].D"/> |
| <pack_pattern name="DSP_P[29:0]-PREG" in_port="mult_25x18.p[29:0]" out_port="PREG[29:0].D"/> |
| <pack_pattern name="DSP_P[28:0]-PREG" in_port="mult_25x18.p[28:0]" out_port="PREG[28:0].D"/> |
| <pack_pattern name="DSP_P[27:0]-PREG" in_port="mult_25x18.p[27:0]" out_port="PREG[27:0].D"/> |
| <pack_pattern name="DSP_P[26:0]-PREG" in_port="mult_25x18.p[26:0]" out_port="PREG[26:0].D"/> |
| <pack_pattern name="DSP_P[25:0]-PREG" in_port="mult_25x18.p[25:0]" out_port="PREG[25:0].D"/> |
| <pack_pattern name="DSP_P[24:0]-PREG" in_port="mult_25x18.p[24:0]" out_port="PREG[24:0].D"/> |
| <pack_pattern name="DSP_P[23:0]-PREG" in_port="mult_25x18.p[23:0]" out_port="PREG[23:0].D"/> |
| <pack_pattern name="DSP_P[22:0]-PREG" in_port="mult_25x18.p[22:0]" out_port="PREG[22:0].D"/> |
| <pack_pattern name="DSP_P[21:0]-PREG" in_port="mult_25x18.p[21:0]" out_port="PREG[21:0].D"/> |
| <pack_pattern name="DSP_P[20:0]-PREG" in_port="mult_25x18.p[20:0]" out_port="PREG[20:0].D"/> |
| <pack_pattern name="DSP_P[19:0]-PREG" in_port="mult_25x18.p[19:0]" out_port="PREG[19:0].D"/> |
| <pack_pattern name="DSP_P[18:0]-PREG" in_port="mult_25x18.p[18:0]" out_port="PREG[18:0].D"/> |
| <pack_pattern name="DSP_P[17:0]-PREG" in_port="mult_25x18.p[17:0]" out_port="PREG[17:0].D"/> |
| <pack_pattern name="DSP_P[16:0]-PREG" in_port="mult_25x18.p[16:0]" out_port="PREG[16:0].D"/> |
| <pack_pattern name="DSP_P[15:0]-PREG" in_port="mult_25x18.p[15:0]" out_port="PREG[15:0].D"/> |
| <pack_pattern name="DSP_P[14:0]-PREG" in_port="mult_25x18.p[14:0]" out_port="PREG[14:0].D"/> |
| <pack_pattern name="DSP_P[13:0]-PREG" in_port="mult_25x18.p[13:0]" out_port="PREG[13:0].D"/> |
| <pack_pattern name="DSP_P[12:0]-PREG" in_port="mult_25x18.p[12:0]" out_port="PREG[12:0].D"/> |
| <pack_pattern name="DSP_P[11:0]-PREG" in_port="mult_25x18.p[11:0]" out_port="PREG[11:0].D"/> |
| <pack_pattern name="DSP_P[10:0]-PREG" in_port="mult_25x18.p[10:0]" out_port="PREG[10:0].D"/> |
| <pack_pattern name="DSP_P[ 9:0]-PREG" in_port="mult_25x18.p[ 9:0]" out_port="PREG[ 9:0].D"/> |
| <pack_pattern name="DSP_P[ 8:0]-PREG" in_port="mult_25x18.p[ 8:0]" out_port="PREG[ 8:0].D"/> |
| <pack_pattern name="DSP_P[ 7:0]-PREG" in_port="mult_25x18.p[ 7:0]" out_port="PREG[ 7:0].D"/> |
| <pack_pattern name="DSP_P[ 6:0]-PREG" in_port="mult_25x18.p[ 6:0]" out_port="PREG[ 6:0].D"/> |
| <pack_pattern name="DSP_P[ 5:0]-PREG" in_port="mult_25x18.p[ 5:0]" out_port="PREG[ 5:0].D"/> |
| <pack_pattern name="DSP_P[ 4:0]-PREG" in_port="mult_25x18.p[ 4:0]" out_port="PREG[ 4:0].D"/> |
| <pack_pattern name="DSP_P[ 3:0]-PREG" in_port="mult_25x18.p[ 3:0]" out_port="PREG[ 3:0].D"/> |
| <pack_pattern name="DSP_P[ 2:0]-PREG" in_port="mult_25x18.p[ 2:0]" out_port="PREG[ 2:0].D"/> |
| <pack_pattern name="DSP_P[ 1:0]-PREG" in_port="mult_25x18.p[ 1:0]" out_port="PREG[ 1:0].D"/> |
| <pack_pattern name="DSP_P[ 0:0]-PREG" in_port="mult_25x18.p[ 0:0]" out_port="PREG[ 0:0].D"/- -> |
| </direct> |
| <direct name="P" input="PREG.Q" output="DSP48E1.P[42:0]" /> |
| <complete name="clk" input="DSP48E1.CLK" output="AREG.clk BREG.clk PREG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="mult_25x18_REGP"> |
| <pb_type name="mult_25x18" blif_model=".subckt multiply" num_pb="1"> |
| <input name="a" num_pins="25" /> |
| <input name="b" num_pins="18" /> |
| <output name="p" num_pins="43"/> |
| <delay_constant max="3.826e-9" in_port="mult_25x18.a" out_port="mult_25x18.p"/> |
| <delay_constant max="3.597e-9" in_port="mult_25x18.b" out_port="mult_25x18.p"/> |
| </pb_type> |
| <pb_type name="AREG" blif_model=".latch" num_pb="25" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D" /> |
| <output name="Q" num_pins="1" port_class="Q" /> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <!- - T_dspdck_a_areg - -> |
| <T_setup value="0.24e-9" port="AREG.D" clock="clk"/> |
| </pb_type> |
| <pb_type name="BREG" blif_model=".latch" num_pb="18" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D" /> |
| <output name="Q" num_pins="1" port_class="Q" /> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <!- - T_dspdck_b_breg - -> |
| <T_setup value="0.28e-9" port="BREG.D" clock="clk"/> |
| </pb_type> |
| <pb_type name="PREG" blif_model=".latch" num_pb="43" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D" /> |
| <output name="Q" num_pins="1" port_class="Q" /> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.33e-9" port="PREG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="A" input="DSP48E1.A[24:0]" output="mult_25x18.a" /> |
| <direct name="B" input="DSP48E1.B[17:0]" output="mult_25x18.b" /> |
| <direct name="PREG" input="mult_25x18.p" output="PREG.D" /> |
| <direct name="P" input="PREG.Q" output="DSP48E1.P[42:0]"/> |
| |
| <complete name="clk" input="DSP48E1.CLK" output="AREG.clk BREG.clk PREG.clk"/> |
| </interconnect> |
| </mode> |
| <!- -mode name="mult_25x18_REGAB"> |
| <pb_type name="mult_25x18" blif_model=".subckt multiply" num_pb="1"> |
| <input name="a" num_pins="25"/> |
| <input name="b" num_pins="18"/> |
| <output name="p" num_pins="43"/> |
| <delay_constant max="3.826e-9" in_port="mult_25x18.a" out_port="mult_25x18.p"/> |
| <delay_constant max="3.597e-9" in_port="mult_25x18.b" out_port="mult_25x18.p"/> |
| </pb_type> |
| <pb_type name="AREG" blif_model=".latch" num_pb="25" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D" /> |
| <output name="Q" num_pins="1" port_class="Q" /> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.24e-9" port="AREG.D" clock="clk"/> |
| <T_clock_to_Q max="0" port="AREG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="BREG" blif_model=".latch" num_pb="18" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D" /> |
| <output name="Q" num_pins="1" port_class="Q" /> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.28e-9" port="BREG.D" clock="clk"/> |
| <T_clock_to_Q max="0" port="BREG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="AREG" input="DSP48E1.A[24:0]" output="AREG.D" /> |
| <direct name="A" input="AREG.Q" output="mult_25x18.a" /> |
| <direct name="BREG" input="DSP48E1.B[17:0]" output="BREG.D" /> |
| <direct name="B" input="BREG.Q" output="mult_25x18.b" /> |
| <direct name="P" input="mult_25x18.p" output="DSP48E1.P[42:0]" /> |
| <complete name="clk" input="DSP48E1.CLK" output="AREG.clk BREG.clk"/> |
| </interconnect> |
| </mode--> |
| <!--mode name="mult_25x18_REGA"> |
| <pb_type name="mult_25x18" blif_model=".subckt multiply" num_pb="1"> |
| <input name="a" num_pins="25"/> |
| <input name="b" num_pins="18"/> |
| <output name="p" num_pins="43"/> |
| <delay_constant max="3.826e-9" in_port="mult_25x18.a" out_port="mult_25x18.p"/> |
| <delay_constant max="3.597e-9" in_port="mult_25x18.b" out_port="mult_25x18.p"/> |
| </pb_type> |
| <pb_type name="AREG" blif_model=".latch" num_pb="25" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D" /> |
| <output name="Q" num_pins="1" port_class="Q" /> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.24e-9" port="AREG.D" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="AREG" input="DSP48E1.A[24:0]" output="AREG.D" /> |
| <direct name="A" input="AREG.Q" output="mult_25x18.a" /> |
| <direct name="B" input="DSP48E1.B[17:0]" output="mult_25x18.b" /> |
| <direct name="P" input="mult_25x18.p" output="DSP48E1.P[42:0]"/> |
| <complete name="clk" input="DSP48E1.CLK" output="AREG.clk" /> |
| </interconnect> |
| </mode> |
| <mode name="mult_25x18_REGB"> |
| <pb_type name="mult_25x18" blif_model=".subckt multiply" num_pb="1"> |
| <input name="a" num_pins="25"/> |
| <input name="b" num_pins="18"/> |
| <output name="p" num_pins="43"/> |
| <delay_constant max="3.826e-9" in_port="mult_25x18.a" out_port="mult_25x18.p"/> |
| <delay_constant max="3.597e-9" in_port="mult_25x18.b" out_port="mult_25x18.p"/> |
| </pb_type> |
| <pb_type name="BREG" blif_model=".latch" num_pb="18" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D" /> |
| <output name="Q" num_pins="1" port_class="Q" /> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.28e-9" port="BREG.D" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="A" input="DSP48E1.A[24:0]" output="mult_25x18.a" /> |
| <direct name="BREG" input="DSP48E1.B[17:0]" output="BREG.D" /> |
| <direct name="B" input="BREG.Q" output="mult_25x18.b" /> |
| <direct name="P" input="mult_25x18.p" output="DSP48E1.P[42:0]"/> |
| <complete name="clk" input="DSP48E1.CLK" output="BREG.clk" /> |
| </interconnect> |
| </mode--> |
| <mode name="mult_25x18_COMB"> |
| <pb_type name="mult_25x18" blif_model=".subckt multiply" num_pb="1"> |
| <input name="a" num_pins="25"/> |
| <input name="b" num_pins="18"/> |
| <output name="p" num_pins="43"/> |
| <delay_constant max="3.826e-9" in_port="mult_25x18.a" out_port="mult_25x18.p"/> |
| <delay_constant max="3.597e-9" in_port="mult_25x18.b" out_port="mult_25x18.p"/> |
| </pb_type> |
| <pb_type name="AREG" blif_model=".latch" num_pb="25" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <!-- T_dspdck_a_areg --> |
| <T_setup value="0.24e-9" port="AREG.D" clock="clk"/> |
| </pb_type> |
| <pb_type name="BREG" blif_model=".latch" num_pb="18" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <!-- T_dspdck_b_breg --> |
| <T_setup value="0.28e-9" port="BREG.D" clock="clk"/> |
| </pb_type> |
| <pb_type name="PREG" blif_model=".latch" num_pb="43" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.33e-9" port="PREG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="A" input="DSP48E1.A[24:0]" output="mult_25x18.a"/> |
| <direct name="B" input="DSP48E1.B[17:0]" output="mult_25x18.b"/> |
| <direct name="P" input="mult_25x18.p" output="DSP48E1.P[42:0]"/> |
| <complete name="clk" input="DSP48E1.CLK" output="AREG.clk BREG.clk PREG.clk"/> |
| </interconnect> |
| </mode> |
| </pb_type> |
| <pb_type name="RAMB36E1"> |
| <!-- These inputs are for FIFO36E1 --> |
| <input name="ADDRARDADDRL" num_pins="16"/> |
| <input name="ADDRARDADDRU" num_pins="15"/> |
| <input name="ADDRBWRADDRL" num_pins="16"/> |
| <input name="ADDRBWRADDRU" num_pins="15"/> |
| <!--input name="DIADIL" num_pins="16"/> |
| <input name="DIADIU" num_pins="16"/> |
| <input name="DIPADIPL" num_pins="2"/> |
| <input name="DIPADIPU" num_pins="2"/--> |
| <input name="DIADI" num_pins="32"/> |
| <input name="DIPADIP" num_pins="4"/> |
| <input name="WEAL" num_pins="4"/> |
| <input name="WEAU" num_pins="4"/> |
| <!--input name="DIBDIL" num_pins="16"/> |
| <input name="DIBDIU" num_pins="16"/> |
| <input name="DIPBDIPL" num_pins="2"/> |
| <input name="DIPBDIPU" num_pins="2"/--> |
| <input name="DIBDI" num_pins="32"/> |
| <input name="DIPBDIP" num_pins="4"/> |
| <input name="WEBWEL" num_pins="8"/> |
| <input name="WEBWEU" num_pins="8"/> |
| <input name="ENARDENL" num_pins="1"/> |
| <input name="ENARDENU" num_pins="1"/> |
| <input name="ENBWRENL" num_pins="1"/> |
| <input name="ENBWRENU" num_pins="1"/> |
| <input name="REGCEAREGCEL" num_pins="1"/> |
| <input name="REGCEAREGCEU" num_pins="1"/> |
| <input name="REGCEBL" num_pins="1"/> |
| <input name="REGCEBU" num_pins="1"/> |
| <input name="RSTRAMARSTRAMLRST" num_pins="1"/> |
| <input name="RSTRAMARSTRAMU" num_pins="1"/> |
| <input name="RSTRAMBL" num_pins="1"/> |
| <input name="RSTRAMBU" num_pins="1"/> |
| <input name="RSTREGARSTREGL" num_pins="1"/> |
| <input name="RSTREGARSTREGU" num_pins="1"/> |
| <input name="RSTREGBL" num_pins="1"/> |
| <input name="RSTREGBU" num_pins="1"/> |
| <!-- These inputs are for the FIFO18E1 slice --> |
| <input name="s0_ADDRARDADDR" num_pins="14"/> |
| <input name="s0_ADDRBWRADDR" num_pins="14"/> |
| <input name="s0_DIADI" num_pins="16"/> |
| <input name="s0_DIPADIP" num_pins="2"/> |
| <input name="s0_WEA" num_pins="4"/> |
| <input name="s0_DIBDI" num_pins="16"/> |
| <input name="s0_DIPBDIP" num_pins="2"/> |
| <input name="s0_WEBWE" num_pins="8"/> |
| <input name="s0_ENARDEN" num_pins="1"/> |
| <input name="s0_ENBWREN" num_pins="1"/> |
| <input name="s0_ADDRATIEHIGH" num_pins="2"/> |
| <input name="s0_ADDRBTIEHIGH" num_pins="2"/> |
| <input name="s0_REGCEAREGCE" num_pins="1"/> |
| <input name="s0_REGCEB" num_pins="1"/> |
| <input name="s0_RSTRAMARSTRAM" num_pins="1"/> |
| <input name="s0_RSTRAMB" num_pins="1"/> |
| <input name="s0_RSTREGARSTREG" num_pins="1"/> |
| <input name="s0_RSTREGB" num_pins="1"/> |
| <!-- These inputs (with underscores) for RAMB18E1 --> |
| <input name="s1_ADDRARDADDR" num_pins="14"/> |
| <input name="s1_ADDRBWRADDR" num_pins="14"/> |
| <input name="s1_DIADI" num_pins="16"/> |
| <input name="s1_DIPADIP" num_pins="2"/> |
| <input name="s1_WEA" num_pins="4"/> |
| <input name="s1_DIBDI" num_pins="16"/> |
| <input name="s1_DIPBDIP" num_pins="2"/> |
| <input name="s1_WEBWE" num_pins="8"/> |
| <input name="s1_ENARDEN" num_pins="1"/> |
| <input name="s1_ENBWREN" num_pins="1"/> |
| <input name="s1_ADDRATIEHIGH" num_pins="2"/> |
| <input name="s1_ADDRBTIEHIGH" num_pins="2"/> |
| <input name="s1_REGCEAREGCE" num_pins="1"/> |
| <input name="s1_REGCEB" num_pins="1"/> |
| <input name="s1_RSTRAMARSTRAM" num_pins="1"/> |
| <input name="s1_RSTRAMB" num_pins="1"/> |
| <input name="s1_RSTREGARSTREG" num_pins="1"/> |
| <input name="s1_RSTREGB" num_pins="1"/> |
| <!--output name ="DOADOL" num_pins="16"/> |
| <output name ="DOADOU" num_pins="16"/> |
| <output name ="DOPADOPL" num_pins="2"/> |
| <output name ="DOPADOPU" num_pins="2"/> |
| <output name ="DOBDOL" num_pins="16"/> |
| <output name ="DOBDOU" num_pins="16"/> |
| <output name ="DOPBDOPL" num_pins="2"/> |
| <output name ="DOPBDOPU" num_pins="2"/--> |
| <output name="DOADO" num_pins="32"/> |
| <output name="DOPADOP" num_pins="4"/> |
| <output name="DOBDO" num_pins="32"/> |
| <output name="DOPBDOP" num_pins="4"/> |
| <output name="s0_DOADO" num_pins="16"/> |
| <output name="s0_DOPADOP" num_pins="2"/> |
| <output name="s0_DOBDO" num_pins="16"/> |
| <output name="s0_DOPBDOP" num_pins="2"/> |
| <output name="s1_DOADO" num_pins="16"/> |
| <output name="s1_DOPADOP" num_pins="2"/> |
| <output name="s1_DOBDO" num_pins="16"/> |
| <output name="s1_DOPBDOP" num_pins="2"/> |
| <!-- 462: --> |
| <output name="GND_WIRE" num_pins="1"/> |
| <output name="VCC_WIRE" num_pins="1"/> |
| <!-- 464: --> |
| <clock name="CLKARDCLKL" num_pins="1"/> |
| <clock name="CLKARDCLKU" num_pins="1"/> |
| <clock name="CLKBWRCLKL" num_pins="1"/> |
| <clock name="CLKBWRCLKU" num_pins="1"/> |
| <clock name="s0_CLKARDCLK" num_pins="1"/> |
| <clock name="s0_CLKBWRCLK" num_pins="1"/> |
| <clock name="s1_CLKARDCLK" num_pins="1"/> |
| <clock name="s1_CLKBWRCLK" num_pins="1"/> |
| <!-- 472: --> |
| <clock name="REGCLKARDRCLKL" num_pins="1"/> |
| <clock name="REGCLKARDRCLKU" num_pins="1"/> |
| <clock name="REGCLKBL" num_pins="1"/> |
| <clock name="REGCLKBU" num_pins="1"/> |
| <clock name="s0_REGCLKARDRCLK" num_pins="1"/> |
| <clock name="s0_REGCLKB" num_pins="1"/> |
| <clock name="s1_REGCLKARDRCLK" num_pins="1"/> |
| <clock name="s1_REGCLKB" num_pins="1"/> |
| <!-- RAMB18E1 --> |
| <mode name="RAMB18E1x2"> |
| <pb_type name="RAMB18E1" num_pb="2"> |
| <input name="ADDRARDADDR" num_pins="14" port_class="addr1"/> |
| <input name="ADDRBWRADDR" num_pins="14" port_class="addr2"/> |
| <input name="DIADI" num_pins="16" port_class="data_in1"/> |
| <input name="DIPADIP" num_pins="2" port_class="data_in1"/> |
| <input name="WEA" num_pins="4" port_class="write_en1"/> |
| <input name="DIBDI" num_pins="16" port_class="data_in2"/> |
| <input name="DIPBDIP" num_pins="2" port_class="data_in2"/> |
| <input name="WEBWE" num_pins="8" port_class="write_en2"/> |
| <output name="DOADO" num_pins="16" port_class="data_out1"/> |
| <output name="DOPADOP" num_pins="2" port_class="data_out1"/> |
| <output name="DOBDO" num_pins="16" port_class="data_out2"/> |
| <output name="DOPBDOP" num_pins="2" port_class="data_out2"/> |
| <clock name="CLKARDCLK" num_pins="1" port_class="clock"/> |
| <clock name="CLKBWRCLK" num_pins="1" port_class="clock"/> |
| <mode name="RAMB18E1_512x36_REGB_sp"> |
| <pb_type name="RAMB18E1_512x36_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="9" port_class="address"/> |
| <input name="data" num_pins="36" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="36" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <!-- TRCE: Trcck_addrb --> |
| <T_setup value="0.480e-9" port="RAMB18E1_512x36_sp.addr" clock="clk"/> |
| <!-- TRCE: Trdck_dib --> |
| <T_setup value="0.707e-9" port="RAMB18E1_512x36_sp.data" clock="clk"/> |
| <!-- TRCE: Trcck_web --> |
| <T_setup value="0.515e-9" port="RAMB18E1_512x36_sp.we" clock="clk"/> |
| <!-- TRCE: Trcko_doa --> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_512x36_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <!-- Trcko_do_reg --> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <!-- Trcko_do_reg --> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB18E1.ADDRBWRADDR[13:5]" output="RAMB18E1_512x36_sp.addr"/> |
| <direct name="data" input="RAMB18E1.DIADI[15:0]" output="RAMB18E1_512x36_sp.data[15:0]"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[15:0]" output="RAMB18E1_512x36_sp.data[31:16]"/> |
| <direct name="datap" input="RAMB18E1.DIPADIP[1:0]" output="RAMB18E1_512x36_sp.data[33:32]"/> |
| <direct name="data2_0" input="RAMB18E1.DIPBDIP[1:0]" output="RAMB18E1_512x36_sp.data[35:34]"/> |
| <direct name="we" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_512x36_sp.we"/> |
| <direct name="dff" input="RAMB18E1_512x36_sp.out" output="DOB_REG[35:0].D"> |
| <!--pack_pattern name="RAMB18E1_512x36_sp_DOB" in_port="RAMB18E1_512x36_sp.out" out_port="DOB_REG.D"/--> |
| </direct> |
| <direct name="out" input="DOB_REG[15: 0].Q" output="RAMB18E1.DOADO[15:0]"/> |
| <direct name="out_1" input="DOB_REG[31:16].Q" output="RAMB18E1.DOBDO[15:0]"/> |
| <direct name="out_2" input="DOB_REG[33:32].Q" output="RAMB18E1.DOPADOP[1:0]"/> |
| <direct name="out_3" input="DOB_REG[35:34].Q" output="RAMB18E1.DOPBDOP[1:0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_512x36_sp.clk[0]"/> |
| <complete name="clk_4" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_512x36_COMB_sp"> |
| <pb_type name="RAMB18E1_512x36_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="9" port_class="address"/> |
| <input name="data" num_pins="36" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="36" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <!-- Trcck_addr --> |
| <T_setup value="0.480e-9" port="RAMB18E1_512x36_sp.addr" clock="clk"/> |
| <!-- Trdck_d --> |
| <T_setup value="0.707e-9" port="RAMB18E1_512x36_sp.data" clock="clk"/> |
| <!-- Trcck_we --> |
| <T_setup value="0.515e-9" port="RAMB18E1_512x36_sp.we" clock="clk"/> |
| <!-- Trcko_do --> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_512x36_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB18E1.ADDRBWRADDR[13:5]" output="RAMB18E1_512x36_sp.addr"/> |
| <direct name="data" input="RAMB18E1.DIADI[15:0]" output="RAMB18E1_512x36_sp.data[15:0]"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[15:0]" output="RAMB18E1_512x36_sp.data[31:16]"/> |
| <direct name="datap" input="RAMB18E1.DIPADIP[1:0]" output="RAMB18E1_512x36_sp.data[33:32]"/> |
| <direct name="data2_0" input="RAMB18E1.DIPBDIP[1:0]" output="RAMB18E1_512x36_sp.data[35:34]"/> |
| <direct name="we" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_512x36_sp.we"/> |
| <direct name="out" input="RAMB18E1_512x36_sp.out[15:0]" output="RAMB18E1.DOADO[15:0]"/> |
| <direct name="out_1" input="RAMB18E1_512x36_sp.out[31:16]" output="RAMB18E1.DOBDO[15:0]"/> |
| <direct name="out_2" input="RAMB18E1_512x36_sp.out[33:32]" output="RAMB18E1.DOPADOP[1:0]"/> |
| <direct name="out_3" input="RAMB18E1_512x36_sp.out[35:34]" output="RAMB18E1.DOPBDOP[1:0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_512x36_sp.clk[0]"/> |
| <complete name="clk_4" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_1024x18_REGB_sp"> |
| <pb_type name="RAMB18E1_1024x18_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="10" port_class="address"/> |
| <input name="data" num_pins="18" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="18" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_1024x18_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_1024x18_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_1024x18_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_1024x18_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="18" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="18" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB18E1.ADDRBWRADDR[13:4]" output="RAMB18E1_1024x18_sp.addr"/> |
| <direct name="data" input="RAMB18E1.DIBDI[15:0]" output="RAMB18E1_1024x18_sp.data[15:0]"/> |
| <direct name="datap" input="RAMB18E1.DIPBDIP[1:0]" output="RAMB18E1_1024x18_sp.data[17:16]"/> |
| <direct name="we" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_1024x18_sp.we"/> |
| <direct name="out" input="RAMB18E1_1024x18_sp.out" output="DOB_REG[17:0].D"> |
| <!--pack_pattern name="RAMB18E1_1024x18_sp_DOB" in_port="RAMB18E1_1024x18_sp.out" out_port="DOB_REG.D"/--> |
| </direct> |
| <direct name="out_0" input="DOB_REG[15: 0].Q" output="RAMB18E1.DOBDO[15:0]"/> |
| <direct name="out_1" input="DOB_REG[17:16].Q" output="RAMB18E1.DOPBDOP[1:0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_1024x18_sp.clk[0]"/> |
| <complete name="clk_2" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_1024x18_COMB_sp"> |
| <pb_type name="RAMB18E1_1024x18_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="10" port_class="address"/> |
| <input name="data" num_pins="18" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="18" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_1024x18_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_1024x18_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_1024x18_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_1024x18_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="18" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="18" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB18E1.ADDRBWRADDR[13:4]" output="RAMB18E1_1024x18_sp.addr"/> |
| <direct name="data" input="RAMB18E1.DIBDI[15:0]" output="RAMB18E1_1024x18_sp.data[15:0]"/> |
| <direct name="datap" input="RAMB18E1.DIPBDIP[1:0]" output="RAMB18E1_1024x18_sp.data[17:16]"/> |
| <direct name="we" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_1024x18_sp.we"/> |
| <direct name="out" input="RAMB18E1_1024x18_sp.out[15:0]" output="RAMB18E1.DOBDO[15:0]"/> |
| <direct name="out_0" input="RAMB18E1_1024x18_sp.out[17:16]" output="RAMB18E1.DOPBDOP[1:0]"/> |
| <complete name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_1024x18_sp.clk[0]"/> |
| <complete name="clk_1" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_2048x9_REGB_sp"> |
| <pb_type name="RAMB18E1_2048x9_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="11" port_class="address"/> |
| <input name="data" num_pins="9" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="9" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_2048x9_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_2048x9_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_2048x9_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_2048x9_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="9" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="9" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB18E1.ADDRBWRADDR[13:3]" output="RAMB18E1_2048x9_sp.addr"/> |
| <direct name="data" input="RAMB18E1.DIBDI[7:0]" output="RAMB18E1_2048x9_sp.data[7:0]"/> |
| <direct name="datap" input="RAMB18E1.DIPBDIP[0]" output="RAMB18E1_2048x9_sp.data[8]"/> |
| <direct name="we" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_2048x9_sp.we"/> |
| <direct name="out" input="RAMB18E1_2048x9_sp.out" output="DOB_REG[8:0].D"> |
| <!--pack_pattern name="RAMB18E1_2048x9_sp_DOB" in_port="RAMB18E1_2048x9_sp.out" out_port="DOB_REG.D"/--> |
| </direct> |
| <direct name="out_0" input="DOB_REG[7:0].Q" output="RAMB18E1.DOBDO[7:0]"/> |
| <direct name="out_1" input="DOB_REG[8].Q" output="RAMB18E1.DOPBDOP[0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_2048x9_sp.clk[0]"/> |
| <complete name="clk_2" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_2048x9_COMB_sp"> |
| <pb_type name="RAMB18E1_2048x9_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="11" port_class="address"/> |
| <input name="data" num_pins="9" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="9" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_2048x9_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_2048x9_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_2048x9_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_2048x9_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="9" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="9" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB18E1.ADDRBWRADDR[13:3]" output="RAMB18E1_2048x9_sp.addr"/> |
| <direct name="data" input="RAMB18E1.DIBDI[7:0]" output="RAMB18E1_2048x9_sp.data[7:0]"/> |
| <direct name="datap" input="RAMB18E1.DIPBDIP[0]" output="RAMB18E1_2048x9_sp.data[8]"/> |
| <direct name="we" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_2048x9_sp.we"/> |
| <direct name="out" input="RAMB18E1_2048x9_sp.out[7:0]" output="RAMB18E1.DOBDO[7:0]"/> |
| <direct name="out_0" input="RAMB18E1_2048x9_sp.out[8]" output="RAMB18E1.DOPBDOP[0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_2048x9_sp.clk[0]"/> |
| <complete name="clk_1" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_4096x4_REGB_sp"> |
| <pb_type name="RAMB18E1_4096x4_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="12" port_class="address"/> |
| <input name="data" num_pins="4" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="4" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_4096x4_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_4096x4_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_4096x4_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_4096x4_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="4" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="4" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB18E1.ADDRBWRADDR[13:2]" output="RAMB18E1_4096x4_sp.addr"/> |
| <direct name="data" input="RAMB18E1.DIBDI[3:0]" output="RAMB18E1_4096x4_sp.data[3:0]"/> |
| <direct name="we" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_4096x4_sp.we"/> |
| <direct name="out" input="RAMB18E1_4096x4_sp.out[3:0]" output="DOB_REG[3:0].D"> |
| <!--pack_pattern name="RAMB18E1_4096x4_sp_DOB" in_port="RAMB18E1_4096x4_sp.out" out_port="DOB_REG.D"/--> |
| </direct> |
| <direct name="out_0" input="DOB_REG[3:0].Q" output="RAMB18E1.DOBDO[3:0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_4096x4_sp.clk[0]"/> |
| <complete name="clk_1" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_4096x4_COMB_sp"> |
| <pb_type name="RAMB18E1_4096x4_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="12" port_class="address"/> |
| <input name="data" num_pins="4" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="4" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_4096x4_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_4096x4_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_4096x4_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_4096x4_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="4" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="4" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB18E1.ADDRBWRADDR[13:2]" output="RAMB18E1_4096x4_sp.addr"/> |
| <direct name="data" input="RAMB18E1.DIBDI[3:0]" output="RAMB18E1_4096x4_sp.data"/> |
| <direct name="we" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_4096x4_sp.we"/> |
| <direct name="out" input="RAMB18E1_4096x4_sp.out" output="RAMB18E1.DOBDO[3:0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_4096x4_sp.clk[0]"/> |
| <complete name="clk_0" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_8192x2_REGB_sp"> |
| <pb_type name="RAMB18E1_8192x2_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="13" port_class="address"/> |
| <input name="data" num_pins="2" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="2" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_8192x2_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_8192x2_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_8192x2_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_8192x2_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="2" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="2" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB18E1.ADDRBWRADDR[13:1]" output="RAMB18E1_8192x2_sp.addr"/> |
| <direct name="data" input="RAMB18E1.DIBDI[1:0]" output="RAMB18E1_8192x2_sp.data"/> |
| <direct name="we" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_8192x2_sp.we"/> |
| <direct name="out" input="RAMB18E1_8192x2_sp.out" output="DOB_REG[1:0].D"> |
| <!--pack_pattern name="RAMB18E1_8192x2_sp_DOB" in_port="RAMB18E1_8192x2_sp.out" out_port="DOB_REG.D"/--> |
| </direct> |
| <direct name="out_0" input="DOB_REG[1:0].Q" output="RAMB18E1.DOBDO[1:0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_8192x2_sp.clk[0]"/> |
| <complete name="clk_1" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_8192x2_COMB_sp"> |
| <pb_type name="RAMB18E1_8192x2_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="13" port_class="address"/> |
| <input name="data" num_pins="2" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="2" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_8192x2_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_8192x2_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_8192x2_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_8192x2_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="2" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="2" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB18E1.ADDRBWRADDR[13:1]" output="RAMB18E1_8192x2_sp.addr"/> |
| <direct name="data" input="RAMB18E1.DIBDI[1:0]" output="RAMB18E1_8192x2_sp.data"/> |
| <direct name="we" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_8192x2_sp.we"/> |
| <direct name="out" input="RAMB18E1_8192x2_sp.out" output="RAMB18E1.DOBDO[1:0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_8192x2_sp.clk[0]"/> |
| <complete name="clk_0" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_16384x1_REGB_sp"> |
| <pb_type name="RAMB18E1_16384x1_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="14" port_class="address"/> |
| <input name="data" num_pins="1" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="1" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_16384x1_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_16384x1_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_16384x1_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_16384x1_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="1" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="1" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB18E1.ADDRBWRADDR[13:0]" output="RAMB18E1_16384x1_sp.addr"/> |
| <direct name="data" input="RAMB18E1.DIBDI[0]" output="RAMB18E1_16384x1_sp.data"/> |
| <direct name="we" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_16384x1_sp.we"/> |
| <direct name="out" input="RAMB18E1_16384x1_sp.out" output="DOB_REG[0].D"> |
| <!--pack_pattern name="RAMB18E1_16384x1_sp_DOB" in_port="RAMB18E1_16384x1_sp.out" out_port="DOB_REG.D"/--> |
| </direct> |
| <direct name="out_0" input="DOB_REG[0].Q" output="RAMB18E1.DOBDO[0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_16384x1_sp.clk[0]"/> |
| <complete name="clk_1" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_16384x1_COMB_sp"> |
| <pb_type name="RAMB18E1_16384x1_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="14" port_class="address"/> |
| <input name="data" num_pins="1" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="1" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_16384x1_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_16384x1_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_16384x1_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_16384x1_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="1" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="1" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB18E1.ADDRBWRADDR[13:0]" output="RAMB18E1_16384x1_sp.addr"/> |
| <direct name="data" input="RAMB18E1.DIBDI[0]" output="RAMB18E1_16384x1_sp.data"/> |
| <direct name="we" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_16384x1_sp.we"/> |
| <direct name="out" input="RAMB18E1_16384x1_sp.out" output="RAMB18E1.DOBDO[0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_16384x1_sp.clk[0]"/> |
| <complete name="clk_0" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <!-- RAMB18E1 Dual-port RAM --> |
| <mode name="RAMB18E1_1024x18_REGAB_dp"> |
| <pb_type name="RAMB18E1_1024x18_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="10" port_class="addr1"/> |
| <input name="addr2" num_pins="10" port_class="addr2"/> |
| <input name="data1" num_pins="18" port_class="data_in1"/> |
| <input name="data2" num_pins="18" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="18" port_class="data_out1"/> |
| <output name="out2" num_pins="18" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_1024x18_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_1024x18_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_1024x18_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_1024x18_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_1024x18_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_1024x18_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_1024x18_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_1024x18_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="18" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="18" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR[13:4]" output="RAMB18E1_1024x18_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR[13:4]" output="RAMB18E1_1024x18_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[15:0]" output="RAMB18E1_1024x18_dp.data1[15:0]"/> |
| <direct name="data1_0" input="RAMB18E1.DIPADIP[1:0]" output="RAMB18E1_1024x18_dp.data1[17:16]"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[15:0]" output="RAMB18E1_1024x18_dp.data2[15:0]"/> |
| <direct name="data2_1" input="RAMB18E1.DIPBDIP[1:0]" output="RAMB18E1_1024x18_dp.data2[17:16]"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_1024x18_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_1024x18_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_1024x18_dp.out1" output="DOA_REG[17:0].D"> |
| <!-- FIXME: This pattern is obsolete because of problem below --> |
| <!--pack_pattern name="RAMB18E1_1024x18_dp_DOA" in_port="RAMB18E1_1024x18_dp.out1" out_port="DOA_REG.D"/--> |
| </direct> |
| <direct name="out1_2" input="DOA_REG[15: 0].Q" output="RAMB18E1.DOADO[15:0]"/> |
| <direct name="out1_3" input="DOA_REG[17:16].Q" output="RAMB18E1.DOPADOP[1:0]"/> |
| <direct name="out2" input="RAMB18E1_1024x18_dp.out2" output="DOB_REG[17:0].D"> |
| <!-- FIXME: For circuit with both DOA_REG and DOB_REG, this pattern is not recognised --> |
| <!--pack_pattern name="RAMB18E1_1024x18_dp_DOB" in_port="RAMB18E1_1024x18_dp.out2" out_port="DOB_REG.D"/--> |
| </direct> |
| <direct name="out2_4" input="DOB_REG[15: 0].Q" output="RAMB18E1.DOBDO[15:0]"/> |
| <direct name="out2_5" input="DOB_REG[17:16].Q" output="RAMB18E1.DOPBDOP[1:0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_1024x18_dp.clk[0]"/> |
| <complete name="clk_6" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_1024x18_REGA_dp"> |
| <pb_type name="RAMB18E1_1024x18_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="10" port_class="addr1"/> |
| <input name="addr2" num_pins="10" port_class="addr2"/> |
| <input name="data1" num_pins="18" port_class="data_in1"/> |
| <input name="data2" num_pins="18" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="18" port_class="data_out1"/> |
| <output name="out2" num_pins="18" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_1024x18_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_1024x18_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_1024x18_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_1024x18_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_1024x18_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_1024x18_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_1024x18_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_1024x18_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="18" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="18" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR[13:4]" output="RAMB18E1_1024x18_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR[13:4]" output="RAMB18E1_1024x18_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[15:0]" output="RAMB18E1_1024x18_dp.data1[15:0]"/> |
| <direct name="data1_0" input="RAMB18E1.DIPADIP[1:0]" output="RAMB18E1_1024x18_dp.data1[17:16]"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[15:0]" output="RAMB18E1_1024x18_dp.data2[15:0]"/> |
| <direct name="data2_1" input="RAMB18E1.DIPBDIP[1:0]" output="RAMB18E1_1024x18_dp.data2[17:16]"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_1024x18_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_1024x18_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_1024x18_dp.out1" output="DOA_REG[17:0].D"> |
| <!--pack_pattern name="RAMB18E1_1024x18_dp_DOA" in_port="RAMB18E1_1024x18_dp.out1" out_port="DOA_REG.D"/--> |
| </direct> |
| <direct name="out1_2" input="DOA_REG[15: 0].Q" output="RAMB18E1.DOADO[15:0]"/> |
| <direct name="out1_3" input="DOA_REG[17:16].Q" output="RAMB18E1.DOPADOP[1:0]"/> |
| <direct name="out2" input="RAMB18E1_1024x18_dp.out2[15:0]" output="RAMB18E1.DOBDO[15:0]"/> |
| <direct name="out2_4" input="RAMB18E1_1024x18_dp.out2[17:16]" output="RAMB18E1.DOPBDOP[1:0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_1024x18_dp.clk[0]"/> |
| <complete name="clk_5" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_1024x18_REGB_dp"> |
| <pb_type name="RAMB18E1_1024x18_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="10" port_class="addr1"/> |
| <input name="addr2" num_pins="10" port_class="addr2"/> |
| <input name="data1" num_pins="18" port_class="data_in1"/> |
| <input name="data2" num_pins="18" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="18" port_class="data_out1"/> |
| <output name="out2" num_pins="18" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_1024x18_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_1024x18_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_1024x18_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_1024x18_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_1024x18_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_1024x18_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_1024x18_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_1024x18_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="18" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="18" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR[13:4]" output="RAMB18E1_1024x18_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR[13:4]" output="RAMB18E1_1024x18_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[15:0]" output="RAMB18E1_1024x18_dp.data1[15:0]"/> |
| <direct name="data1_0" input="RAMB18E1.DIPADIP[1:0]" output="RAMB18E1_1024x18_dp.data1[17:16]"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[15:0]" output="RAMB18E1_1024x18_dp.data2[15:0]"/> |
| <direct name="data2_1" input="RAMB18E1.DIPBDIP[1:0]" output="RAMB18E1_1024x18_dp.data2[17:16]"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_1024x18_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_1024x18_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_1024x18_dp.out1[15:0]" output="RAMB18E1.DOADO[15:0]"/> |
| <direct name="out1_2" input="RAMB18E1_1024x18_dp.out1[17:16]" output="RAMB18E1.DOPADOP[1:0]"/> |
| <direct name="out2" input="RAMB18E1_1024x18_dp.out2" output="DOB_REG[17:0].D"> |
| <!-- FIXME: For circuit with just DOB_REG, this pattern is recognised, |
| but VPR cannot find any logic block to implement the resulting molecule --> |
| <!--pack_pattern name="RAMB18E1_1024x18_dp_DOB" in_port="RAMB18E1_1024x18_dp.out2" out_port="DOB_REG.D"/--> |
| </direct> |
| <direct name="out2_3" input="DOB_REG[15: 0].Q" output="RAMB18E1.DOBDO[15:0]"/> |
| <direct name="out2_4" input="DOB_REG[17:16].Q" output="RAMB18E1.DOPBDOP[1:0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_1024x18_dp.clk[0]"/> |
| <complete name="clk_5" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_1024x18_COMB_dp"> |
| <pb_type name="RAMB18E1_1024x18_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="10" port_class="addr1"/> |
| <input name="addr2" num_pins="10" port_class="addr2"/> |
| <input name="data1" num_pins="18" port_class="data_in1"/> |
| <input name="data2" num_pins="18" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="18" port_class="data_out1"/> |
| <output name="out2" num_pins="18" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_1024x18_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_1024x18_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_1024x18_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_1024x18_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_1024x18_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_1024x18_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_1024x18_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_1024x18_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="18" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="18" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR[13:4]" output="RAMB18E1_1024x18_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR[13:4]" output="RAMB18E1_1024x18_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[15:0]" output="RAMB18E1_1024x18_dp.data1[15:0]"/> |
| <direct name="data1_0" input="RAMB18E1.DIPADIP[1:0]" output="RAMB18E1_1024x18_dp.data1[17:16]"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[15:0]" output="RAMB18E1_1024x18_dp.data2[15:0]"/> |
| <direct name="data2_1" input="RAMB18E1.DIPBDIP[1:0]" output="RAMB18E1_1024x18_dp.data2[17:16]"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_1024x18_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_1024x18_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_1024x18_dp.out1[15:0]" output="RAMB18E1.DOADO[15:0]"/> |
| <direct name="out1_2" input="RAMB18E1_1024x18_dp.out1[17:16]" output="RAMB18E1.DOPADOP[1:0]"/> |
| <direct name="out2" input="RAMB18E1_1024x18_dp.out2[15:0]" output="RAMB18E1.DOBDO[15:0]"/> |
| <direct name="out2_3" input="RAMB18E1_1024x18_dp.out2[17:16]" output="RAMB18E1.DOPBDOP[1:0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_1024x18_dp.clk[0]"/> |
| <complete name="clk_4" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_2048x9_REGAB_dp"> |
| <pb_type name="RAMB18E1_2048x9_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="11" port_class="addr1"/> |
| <input name="addr2" num_pins="11" port_class="addr2"/> |
| <input name="data1" num_pins="9" port_class="data_in1"/> |
| <input name="data2" num_pins="9" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="9" port_class="data_out1"/> |
| <output name="out2" num_pins="9" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_2048x9_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_2048x9_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_2048x9_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_2048x9_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_2048x9_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_2048x9_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_2048x9_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_2048x9_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="9" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="9" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR[13:3]" output="RAMB18E1_2048x9_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR[13:3]" output="RAMB18E1_2048x9_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[7:0]" output="RAMB18E1_2048x9_dp.data1[7:0]"/> |
| <direct name="data1_0" input="RAMB18E1.DIPADIP[0]" output="RAMB18E1_2048x9_dp.data1[8]"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[7:0]" output="RAMB18E1_2048x9_dp.data2[7:0]"/> |
| <direct name="data2_1" input="RAMB18E1.DIPBDIP[0]" output="RAMB18E1_2048x9_dp.data2[8]"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_2048x9_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_2048x9_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_2048x9_dp.out1" output="DOA_REG[8:0].D"/> |
| <direct name="out1_2" input="DOA_REG[7:0].Q" output="RAMB18E1.DOADO[7:0]"/> |
| <direct name="out1_3" input="DOA_REG[8].Q" output="RAMB18E1.DOPADOP[0]"/> |
| <direct name="out2" input="RAMB18E1_2048x9_dp.out2" output="DOB_REG[8:0].D"/> |
| <direct name="out2_4" input="DOB_REG[7:0].Q" output="RAMB18E1.DOBDO[7:0]"/> |
| <direct name="out2_5" input="DOB_REG[8].Q" output="RAMB18E1.DOPBDOP[0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_2048x9_dp.clk[0]"/> |
| <complete name="clk_6" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_2048x9_REGA_dp"> |
| <pb_type name="RAMB18E1_2048x9_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="11" port_class="addr1"/> |
| <input name="addr2" num_pins="11" port_class="addr2"/> |
| <input name="data1" num_pins="9" port_class="data_in1"/> |
| <input name="data2" num_pins="9" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="9" port_class="data_out1"/> |
| <output name="out2" num_pins="9" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_2048x9_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_2048x9_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_2048x9_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_2048x9_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_2048x9_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_2048x9_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_2048x9_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_2048x9_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="9" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="9" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR[13:3]" output="RAMB18E1_2048x9_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR[13:3]" output="RAMB18E1_2048x9_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[7:0]" output="RAMB18E1_2048x9_dp.data1[7:0]"/> |
| <direct name="data1_0" input="RAMB18E1.DIPADIP[0]" output="RAMB18E1_2048x9_dp.data1[8]"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[7:0]" output="RAMB18E1_2048x9_dp.data2[7:0]"/> |
| <direct name="data2_1" input="RAMB18E1.DIPBDIP[0]" output="RAMB18E1_2048x9_dp.data2[8]"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_2048x9_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_2048x9_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_2048x9_dp.out1" output="DOA_REG[8:0].D"> |
| <!--pack_pattern name="RAMB18E1_2048x9_dp_DOA" in_port="RAMB18E1_2048x9_dp.out1" out_port="DOA_REG.D"/--> |
| </direct> |
| <direct name="out1_2" input="DOA_REG[7:0].Q" output="RAMB18E1.DOADO[7:0]"/> |
| <direct name="out1_3" input="DOA_REG[8].Q" output="RAMB18E1.DOPADOP[0]"/> |
| <direct name="out2" input="RAMB18E1_2048x9_dp.out2[7:0]" output="RAMB18E1.DOBDO[7:0]"/> |
| <direct name="out2_4" input="RAMB18E1_2048x9_dp.out2[8]" output="RAMB18E1.DOPBDOP[0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_2048x9_dp.clk[0]"/> |
| <complete name="clk_5" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_2048x9_REGB_dp"> |
| <pb_type name="RAMB18E1_2048x9_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="11" port_class="addr1"/> |
| <input name="addr2" num_pins="11" port_class="addr2"/> |
| <input name="data1" num_pins="9" port_class="data_in1"/> |
| <input name="data2" num_pins="9" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="9" port_class="data_out1"/> |
| <output name="out2" num_pins="9" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_2048x9_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_2048x9_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_2048x9_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_2048x9_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_2048x9_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_2048x9_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_2048x9_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_2048x9_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="9" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="9" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR[13:3]" output="RAMB18E1_2048x9_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR[13:3]" output="RAMB18E1_2048x9_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[7:0]" output="RAMB18E1_2048x9_dp.data1[7:0]"/> |
| <direct name="data1_0" input="RAMB18E1.DIPADIP[0]" output="RAMB18E1_2048x9_dp.data1[8]"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[7:0]" output="RAMB18E1_2048x9_dp.data2[7:0]"/> |
| <direct name="data2_1" input="RAMB18E1.DIPBDIP[0]" output="RAMB18E1_2048x9_dp.data2[8]"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_2048x9_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_2048x9_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_2048x9_dp.out1[7:0]" output="RAMB18E1.DOADO[7:0]"/> |
| <direct name="out1_2" input="RAMB18E1_2048x9_dp.out1[8]" output="RAMB18E1.DOPADOP[0]"/> |
| <direct name="out2" input="RAMB18E1_2048x9_dp.out2" output="DOB_REG[8:0].D"/> |
| <direct name="out2_3" input="DOB_REG[7:0].Q" output="RAMB18E1.DOBDO[7:0]"/> |
| <direct name="out2_4" input="DOB_REG[8].Q" output="RAMB18E1.DOPBDOP[0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_2048x9_dp.clk[0]"/> |
| <complete name="clk_5" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_2048x9_COMB_dp"> |
| <pb_type name="RAMB18E1_2048x9_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="11" port_class="addr1"/> |
| <input name="addr2" num_pins="11" port_class="addr2"/> |
| <input name="data1" num_pins="9" port_class="data_in1"/> |
| <input name="data2" num_pins="9" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="9" port_class="data_out1"/> |
| <output name="out2" num_pins="9" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_2048x9_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_2048x9_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_2048x9_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_2048x9_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_2048x9_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_2048x9_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_2048x9_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_2048x9_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="9" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="9" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR[13:3]" output="RAMB18E1_2048x9_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR[13:3]" output="RAMB18E1_2048x9_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[7:0]" output="RAMB18E1_2048x9_dp.data1[7:0]"/> |
| <direct name="data1_0" input="RAMB18E1.DIPADIP[0]" output="RAMB18E1_2048x9_dp.data1[8]"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[7:0]" output="RAMB18E1_2048x9_dp.data2[7:0]"/> |
| <direct name="data2_1" input="RAMB18E1.DIPBDIP[0]" output="RAMB18E1_2048x9_dp.data2[8]"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_2048x9_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_2048x9_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_2048x9_dp.out1[7:0]" output="RAMB18E1.DOADO[7:0]"/> |
| <direct name="out1_2" input="RAMB18E1_2048x9_dp.out1[8]" output="RAMB18E1.DOPADOP[0]"/> |
| <direct name="out2" input="RAMB18E1_2048x9_dp.out2[7:0]" output="RAMB18E1.DOBDO[7:0]"/> |
| <direct name="out2_3" input="RAMB18E1_2048x9_dp.out2[8]" output="RAMB18E1.DOPBDOP[0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_2048x9_dp.clk[0]"/> |
| <complete name="clk_4" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_4096x4_REGAB_dp"> |
| <pb_type name="RAMB18E1_4096x4_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="12" port_class="addr1"/> |
| <input name="addr2" num_pins="12" port_class="addr2"/> |
| <input name="data1" num_pins="4" port_class="data_in1"/> |
| <input name="data2" num_pins="4" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="4" port_class="data_out1"/> |
| <output name="out2" num_pins="4" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_4096x4_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_4096x4_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_4096x4_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_4096x4_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_4096x4_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_4096x4_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_4096x4_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_4096x4_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="4" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="4" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR[13:2]" output="RAMB18E1_4096x4_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR[13:2]" output="RAMB18E1_4096x4_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[3:0]" output="RAMB18E1_4096x4_dp.data1"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[3:0]" output="RAMB18E1_4096x4_dp.data2"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_4096x4_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_4096x4_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_4096x4_dp.out1" output="DOA_REG[3:0].D"/> |
| <direct name="out1_0" input="DOA_REG[3:0].Q" output="RAMB18E1.DOADO[3:0]"/> |
| <direct name="out2" input="RAMB18E1_4096x4_dp.out2" output="DOB_REG[3:0].D"/> |
| <direct name="out2_1" input="DOB_REG[3:0].Q" output="RAMB18E1.DOBDO[3:0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_4096x4_dp.clk[0]"/> |
| <complete name="clk_2" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_4096x4_REGA_dp"> |
| <pb_type name="RAMB18E1_4096x4_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="12" port_class="addr1"/> |
| <input name="addr2" num_pins="12" port_class="addr2"/> |
| <input name="data1" num_pins="4" port_class="data_in1"/> |
| <input name="data2" num_pins="4" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="4" port_class="data_out1"/> |
| <output name="out2" num_pins="4" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_4096x4_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_4096x4_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_4096x4_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_4096x4_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_4096x4_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_4096x4_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_4096x4_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_4096x4_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="4" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="4" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR[13:2]" output="RAMB18E1_4096x4_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR[13:2]" output="RAMB18E1_4096x4_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[3:0]" output="RAMB18E1_4096x4_dp.data1"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[3:0]" output="RAMB18E1_4096x4_dp.data2"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_4096x4_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_4096x4_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_4096x4_dp.out1" output="DOA_REG[3:0].D"> |
| <!--pack_pattern name="RAMB18E1_4096x4_dp_DOA" in_port="RAMB18E1_4096x4_dp.out1" out_port="DOA_REG.D"/--> |
| </direct> |
| <direct name="out1_0" input="DOA_REG[3:0].Q" output="RAMB18E1.DOADO[3:0]"/> |
| <direct name="out2" input="RAMB18E1_4096x4_dp.out2" output="RAMB18E1.DOBDO[3:0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_4096x4_dp.clk[0]"/> |
| <complete name="clk_1" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_4096x4_REGB_dp"> |
| <pb_type name="RAMB18E1_4096x4_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="12" port_class="addr1"/> |
| <input name="addr2" num_pins="12" port_class="addr2"/> |
| <input name="data1" num_pins="4" port_class="data_in1"/> |
| <input name="data2" num_pins="4" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="4" port_class="data_out1"/> |
| <output name="out2" num_pins="4" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_4096x4_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_4096x4_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_4096x4_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_4096x4_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_4096x4_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_4096x4_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_4096x4_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_4096x4_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="4" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="4" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR[13:2]" output="RAMB18E1_4096x4_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR[13:2]" output="RAMB18E1_4096x4_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[3:0]" output="RAMB18E1_4096x4_dp.data1"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[3:0]" output="RAMB18E1_4096x4_dp.data2"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_4096x4_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_4096x4_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_4096x4_dp.out1" output="RAMB18E1.DOADO[3:0]"/> |
| <direct name="out2" input="RAMB18E1_4096x4_dp.out2" output="DOB_REG[3:0].D"/> |
| <direct name="out2_0" input="DOB_REG[3:0].Q" output="RAMB18E1.DOBDO[3:0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_4096x4_dp.clk[0]"/> |
| <complete name="clk_1" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_4096x4_COMB_dp"> |
| <pb_type name="RAMB18E1_4096x4_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="12" port_class="addr1"/> |
| <input name="addr2" num_pins="12" port_class="addr2"/> |
| <input name="data1" num_pins="4" port_class="data_in1"/> |
| <input name="data2" num_pins="4" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="4" port_class="data_out1"/> |
| <output name="out2" num_pins="4" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_4096x4_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_4096x4_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_4096x4_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_4096x4_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_4096x4_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_4096x4_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_4096x4_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_4096x4_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="4" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="4" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR[13:2]" output="RAMB18E1_4096x4_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR[13:2]" output="RAMB18E1_4096x4_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[3:0]" output="RAMB18E1_4096x4_dp.data1"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[3:0]" output="RAMB18E1_4096x4_dp.data2"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_4096x4_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_4096x4_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_4096x4_dp.out1" output="RAMB18E1.DOADO[3:0]"/> |
| <direct name="out2" input="RAMB18E1_4096x4_dp.out2" output="RAMB18E1.DOBDO[3:0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_4096x4_dp.clk[0]"/> |
| <complete name="clk_0" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_8192x2_REGAB_dp"> |
| <pb_type name="RAMB18E1_8192x2_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="13" port_class="addr1"/> |
| <input name="addr2" num_pins="13" port_class="addr2"/> |
| <input name="data1" num_pins="2" port_class="data_in1"/> |
| <input name="data2" num_pins="2" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="2" port_class="data_out1"/> |
| <output name="out2" num_pins="2" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_8192x2_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_8192x2_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_8192x2_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_8192x2_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_8192x2_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_8192x2_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_8192x2_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_8192x2_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="2" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="2" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR[13:1]" output="RAMB18E1_8192x2_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR[13:1]" output="RAMB18E1_8192x2_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[1:0]" output="RAMB18E1_8192x2_dp.data1"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[1:0]" output="RAMB18E1_8192x2_dp.data2"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_8192x2_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_8192x2_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_8192x2_dp.out1" output="DOA_REG[1:0].D"/> |
| <direct name="out1_0" input="DOA_REG[1:0].Q" output="RAMB18E1.DOADO[1:0]"/> |
| <direct name="out2" input="RAMB18E1_8192x2_dp.out2" output="DOB_REG[1:0].D"/> |
| <direct name="out2_1" input="DOB_REG[1:0].Q" output="RAMB18E1.DOBDO[1:0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_8192x2_dp.clk[0]"/> |
| <complete name="clk_2" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_8192x2_REGA_dp"> |
| <pb_type name="RAMB18E1_8192x2_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="13" port_class="addr1"/> |
| <input name="addr2" num_pins="13" port_class="addr2"/> |
| <input name="data1" num_pins="2" port_class="data_in1"/> |
| <input name="data2" num_pins="2" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="2" port_class="data_out1"/> |
| <output name="out2" num_pins="2" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_8192x2_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_8192x2_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_8192x2_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_8192x2_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_8192x2_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_8192x2_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_8192x2_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_8192x2_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="2" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="2" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR[13:1]" output="RAMB18E1_8192x2_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR[13:1]" output="RAMB18E1_8192x2_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[1:0]" output="RAMB18E1_8192x2_dp.data1"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[1:0]" output="RAMB18E1_8192x2_dp.data2"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_8192x2_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_8192x2_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_8192x2_dp.out1" output="DOA_REG[1:0].D"/> |
| <direct name="out1_0" input="DOA_REG[1:0].Q" output="RAMB18E1.DOADO[1:0]"> |
| <!--pack_pattern name="RAMB18E1_8192x2_dp_DOA" in_port="RAMB18E1_8192x2_dp.out1" out_port="DOA_REG.D"/--> |
| </direct> |
| <direct name="out2" input="RAMB18E1_8192x2_dp.out2" output="RAMB18E1.DOBDO[1:0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_8192x2_dp.clk[0]"/> |
| <complete name="clk_1" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_8192x2_REGB_dp"> |
| <pb_type name="RAMB18E1_8192x2_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="13" port_class="addr1"/> |
| <input name="addr2" num_pins="13" port_class="addr2"/> |
| <input name="data1" num_pins="2" port_class="data_in1"/> |
| <input name="data2" num_pins="2" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="2" port_class="data_out1"/> |
| <output name="out2" num_pins="2" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_8192x2_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_8192x2_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_8192x2_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_8192x2_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_8192x2_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_8192x2_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_8192x2_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_8192x2_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="2" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="2" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR[13:1]" output="RAMB18E1_8192x2_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR[13:1]" output="RAMB18E1_8192x2_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[1:0]" output="RAMB18E1_8192x2_dp.data1"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[1:0]" output="RAMB18E1_8192x2_dp.data2"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_8192x2_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_8192x2_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_8192x2_dp.out1" output="RAMB18E1.DOADO[1:0]"/> |
| <direct name="out2" input="RAMB18E1_8192x2_dp.out2" output="DOB_REG[1:0].D"/> |
| <direct name="out2_0" input="DOB_REG[1:0].Q" output="RAMB18E1.DOBDO[1:0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_8192x2_dp.clk[0]"/> |
| <complete name="clk_1" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_8192x2_COMB_dp"> |
| <pb_type name="RAMB18E1_8192x2_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="13" port_class="addr1"/> |
| <input name="addr2" num_pins="13" port_class="addr2"/> |
| <input name="data1" num_pins="2" port_class="data_in1"/> |
| <input name="data2" num_pins="2" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="2" port_class="data_out1"/> |
| <output name="out2" num_pins="2" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_8192x2_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_8192x2_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_8192x2_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_8192x2_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_8192x2_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_8192x2_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_8192x2_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_8192x2_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="2" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="2" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR[13:1]" output="RAMB18E1_8192x2_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR[13:1]" output="RAMB18E1_8192x2_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[1:0]" output="RAMB18E1_8192x2_dp.data1"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[1:0]" output="RAMB18E1_8192x2_dp.data2"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_8192x2_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_8192x2_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_8192x2_dp.out1" output="RAMB18E1.DOADO[1:0]"/> |
| <direct name="out2" input="RAMB18E1_8192x2_dp.out2" output="RAMB18E1.DOBDO[1:0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_8192x2_dp.clk[0]"/> |
| <complete name="clk_0" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_16384x1_REGAB_dp"> |
| <pb_type name="RAMB18E1_16384x1_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="14" port_class="addr1"/> |
| <input name="addr2" num_pins="14" port_class="addr2"/> |
| <input name="data1" num_pins="1" port_class="data_in1"/> |
| <input name="data2" num_pins="1" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="1" port_class="data_out1"/> |
| <output name="out2" num_pins="1" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_16384x1_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_16384x1_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_16384x1_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_16384x1_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_16384x1_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_16384x1_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_16384x1_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_16384x1_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="1" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="1" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR" output="RAMB18E1_16384x1_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR" output="RAMB18E1_16384x1_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[0]" output="RAMB18E1_16384x1_dp.data1"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[0]" output="RAMB18E1_16384x1_dp.data2"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_16384x1_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_16384x1_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_16384x1_dp.out1" output="DOA_REG[0].D"/> |
| <direct name="out1_0" input="DOA_REG[0].Q" output="RAMB18E1.DOADO[0]"/> |
| <direct name="out2" input="RAMB18E1_16384x1_dp.out2" output="DOB_REG[0].D"/> |
| <direct name="out2_1" input="DOB_REG[0].Q" output="RAMB18E1.DOBDO[0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_16384x1_dp.clk[0]"/> |
| <complete name="clk_2" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_16384x1_REGA_dp"> |
| <pb_type name="RAMB18E1_16384x1_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="14" port_class="addr1"/> |
| <input name="addr2" num_pins="14" port_class="addr2"/> |
| <input name="data1" num_pins="1" port_class="data_in1"/> |
| <input name="data2" num_pins="1" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="1" port_class="data_out1"/> |
| <output name="out2" num_pins="1" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_16384x1_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_16384x1_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_16384x1_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_16384x1_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_16384x1_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_16384x1_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_16384x1_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_16384x1_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="1" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="1" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR" output="RAMB18E1_16384x1_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR" output="RAMB18E1_16384x1_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[0]" output="RAMB18E1_16384x1_dp.data1"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[0]" output="RAMB18E1_16384x1_dp.data2"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_16384x1_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_16384x1_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_16384x1_dp.out1" output="DOA_REG[0].D"> |
| <!--pack_pattern name="RAMB18E1_16384x2_dp_DOA" in_port="RAMB18E1_16384x1_dp.out1" out_port="DOA_REG.D"/--> |
| </direct> |
| <direct name="out1_0" input="DOA_REG[0].Q" output="RAMB18E1.DOADO[0]"/> |
| <direct name="out2" input="RAMB18E1_16384x1_dp.out2" output="RAMB18E1.DOBDO[0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_16384x1_dp.clk[0]"/> |
| <complete name="clk_1" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_16384x1_REGB_dp"> |
| <pb_type name="RAMB18E1_16384x1_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="14" port_class="addr1"/> |
| <input name="addr2" num_pins="14" port_class="addr2"/> |
| <input name="data1" num_pins="1" port_class="data_in1"/> |
| <input name="data2" num_pins="1" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="1" port_class="data_out1"/> |
| <output name="out2" num_pins="1" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_16384x1_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_16384x1_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_16384x1_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_16384x1_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_16384x1_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_16384x1_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_16384x1_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_16384x1_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="1" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="1" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR" output="RAMB18E1_16384x1_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR" output="RAMB18E1_16384x1_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[0]" output="RAMB18E1_16384x1_dp.data1"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[0]" output="RAMB18E1_16384x1_dp.data2"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_16384x1_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_16384x1_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_16384x1_dp.out1" output="RAMB18E1.DOADO[0]"/> |
| <direct name="out2" input="RAMB18E1_16384x1_dp.out2" output="DOB_REG[0].D"/> |
| <direct name="out2_0" input="DOB_REG[0].Q" output="RAMB18E1.DOBDO[0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_16384x1_dp.clk[0]"/> |
| <complete name="clk_1" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB18E1_16384x1_COMB_dp"> |
| <pb_type name="RAMB18E1_16384x1_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="14" port_class="addr1"/> |
| <input name="addr2" num_pins="14" port_class="addr2"/> |
| <input name="data1" num_pins="1" port_class="data_in1"/> |
| <input name="data2" num_pins="1" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="1" port_class="data_out1"/> |
| <output name="out2" num_pins="1" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_16384x1_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_16384x1_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_16384x1_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB18E1_16384x1_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB18E1_16384x1_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB18E1_16384x1_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_16384x1_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB18E1_16384x1_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="1" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="1" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB18E1.ADDRARDADDR" output="RAMB18E1_16384x1_dp.addr1"/> |
| <direct name="addr2" input="RAMB18E1.ADDRBWRADDR" output="RAMB18E1_16384x1_dp.addr2"/> |
| <direct name="data1" input="RAMB18E1.DIADI[0]" output="RAMB18E1_16384x1_dp.data1"/> |
| <direct name="data2" input="RAMB18E1.DIBDI[0]" output="RAMB18E1_16384x1_dp.data2"/> |
| <direct name="we1" input="RAMB18E1.WEA[0]" output="RAMB18E1_16384x1_dp.we1"/> |
| <direct name="we2" input="RAMB18E1.WEBWE[0]" output="RAMB18E1_16384x1_dp.we2"/> |
| <direct name="out1" input="RAMB18E1_16384x1_dp.out1" output="RAMB18E1.DOADO[0]"/> |
| <direct name="out2" input="RAMB18E1_16384x1_dp.out2" output="RAMB18E1.DOBDO[0]"/> |
| <direct name="clk" input="RAMB18E1.CLKARDCLK" output="RAMB18E1_16384x1_dp.clk[0]"/> |
| <complete name="clk_0" input="RAMB18E1.CLKARDCLK" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.s0_ADDRARDADDR" output="RAMB18E1[0].ADDRARDADDR"/> |
| <direct name="addr2" input="RAMB36E1.s0_ADDRBWRADDR" output="RAMB18E1[0].ADDRBWRADDR"/> |
| <direct name="data1" input="RAMB36E1.s0_DIADI" output="RAMB18E1[0].DIADI"/> |
| <direct name="data2" input="RAMB36E1.s0_DIBDI" output="RAMB18E1[0].DIBDI"/> |
| <direct name="data1_0" input="RAMB36E1.s0_DIPADIP" output="RAMB18E1[0].DIPADIP"/> |
| <direct name="data2_1" input="RAMB36E1.s0_DIPBDIP" output="RAMB18E1[0].DIPBDIP"/> |
| <direct name="we1" input="RAMB36E1.s0_WEA" output="RAMB18E1[0].WEA"/> |
| <direct name="we2" input="RAMB36E1.s0_WEBWE" output="RAMB18E1[0].WEBWE"/> |
| <direct name="out1" input="RAMB18E1[0].DOADO" output="RAMB36E1.s0_DOADO"/> |
| <direct name="out1p" input="RAMB18E1[0].DOPADOP" output="RAMB36E1.s0_DOPADOP"/> |
| <direct name="out2" input="RAMB18E1[0].DOBDO" output="RAMB36E1.s0_DOBDO"/> |
| <direct name="out2p" input="RAMB18E1[0].DOPBDOP" output="RAMB36E1.s0_DOPBDOP"/> |
| <direct name="clk" input="RAMB36E1.s0_CLKARDCLK" output="RAMB18E1[0].CLKARDCLK"/> |
| <direct name="clk_2" input="RAMB36E1.s0_CLKBWRCLK" output="RAMB18E1[0].CLKBWRCLK"/> |
| <direct name="addr1_3" input="RAMB36E1.s1_ADDRARDADDR" output="RAMB18E1[1].ADDRARDADDR"/> |
| <direct name="addr2_4" input="RAMB36E1.s1_ADDRBWRADDR" output="RAMB18E1[1].ADDRBWRADDR"/> |
| <direct name="data1_5" input="RAMB36E1.s1_DIADI" output="RAMB18E1[1].DIADI"/> |
| <direct name="data2_6" input="RAMB36E1.s1_DIBDI" output="RAMB18E1[1].DIBDI"/> |
| <direct name="data1_7" input="RAMB36E1.s1_DIPADIP" output="RAMB18E1[1].DIPADIP"/> |
| <direct name="data2_8" input="RAMB36E1.s1_DIPBDIP" output="RAMB18E1[1].DIPBDIP"/> |
| <direct name="we1_9" input="RAMB36E1.s1_WEA" output="RAMB18E1[1].WEA"/> |
| <direct name="we2_10" input="RAMB36E1.s1_WEBWE" output="RAMB18E1[1].WEBWE"/> |
| <direct name="out1_11" input="RAMB18E1[1].DOADO" output="RAMB36E1.s1_DOADO"/> |
| <direct name="out1p_12" input="RAMB18E1[1].DOPADOP" output="RAMB36E1.s1_DOPADOP"/> |
| <direct name="out2_13" input="RAMB18E1[1].DOBDO" output="RAMB36E1.s1_DOBDO"/> |
| <direct name="out2p_14" input="RAMB18E1[1].DOPBDOP" output="RAMB36E1.s1_DOPBDOP"/> |
| <direct name="clk_15" input="RAMB36E1.s1_CLKARDCLK" output="RAMB18E1[1].CLKARDCLK"/> |
| <direct name="clk_16" input="RAMB36E1.s1_CLKBWRCLK" output="RAMB18E1[1].CLKBWRCLK"/> |
| </interconnect> |
| </mode> |
| <!-- RAMB36E1 --> |
| <mode name="RAMB36E1_512x72_REGB_sp"> |
| <pb_type name="RAMB36E1_512x72_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="9" port_class="address"/> |
| <input name="data" num_pins="72" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="72" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_512x72_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_512x72_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_512x72_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_512x72_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB36E1.ADDRBWRADDRL[14:6]" output="RAMB36E1_512x72_sp.addr"/> |
| <direct name="data" input="RAMB36E1.DIADI[31:0]" output="RAMB36E1_512x72_sp.data[31:0]"/> |
| <direct name="data_0" input="RAMB36E1.DIBDI[31:0]" output="RAMB36E1_512x72_sp.data[63:32]"/> |
| <direct name="data_1" input="RAMB36E1.DIPADIP[3:0]" output="RAMB36E1_512x72_sp.data[67:64]"/> |
| <direct name="data_2" input="RAMB36E1.DIPBDIP[3:0]" output="RAMB36E1_512x72_sp.data[71:68]"/> |
| <direct name="out" input="RAMB36E1_512x72_sp.out[31:0]" output="DOA_REG[31:0].D"/> |
| <direct name="out_3" input="RAMB36E1_512x72_sp.out[63:32]" output="DOB_REG[31:0].D"/> |
| <direct name="out_4" input="RAMB36E1_512x72_sp.out[67:64]" output="DOA_REG[35:32].D"/> |
| <direct name="out_5" input="RAMB36E1_512x72_sp.out[71:68]" output="DOB_REG[35:32].D"/> |
| <direct name="out_6" input="DOA_REG[31:0].Q" output="RAMB36E1.DOADO[31:0]"/> |
| <direct name="out_7" input="DOB_REG[31:0].Q" output="RAMB36E1.DOBDO[31:0]"/> |
| <direct name="outp" input="DOA_REG[35:32].Q" output="RAMB36E1.DOPADOP[3:0]"/> |
| <direct name="outp_8" input="DOB_REG[35:32].Q" output="RAMB36E1.DOPBDOP[3:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_512x72_sp.clk[0]"/> |
| <complete name="clk_9" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_512x72_COMB_sp"> |
| <pb_type name="RAMB36E1_512x72_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="9" port_class="address"/> |
| <input name="data" num_pins="72" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="72" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_512x72_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_512x72_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_512x72_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_512x72_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB36E1.ADDRBWRADDRL[14:6]" output="RAMB36E1_512x72_sp.addr"/> |
| <direct name="data" input="RAMB36E1.DIADI[31:0]" output="RAMB36E1_512x72_sp.data[31:0]"/> |
| <direct name="data_0" input="RAMB36E1.DIBDI[31:0]" output="RAMB36E1_512x72_sp.data[63:32]"/> |
| <direct name="data_1" input="RAMB36E1.DIPADIP[3:0]" output="RAMB36E1_512x72_sp.data[67:64]"/> |
| <direct name="data_2" input="RAMB36E1.DIPBDIP[3:0]" output="RAMB36E1_512x72_sp.data[71:68]"/> |
| <direct name="out" input="RAMB36E1_512x72_sp.out[31:0]" output="RAMB36E1.DOADO[31:0]"/> |
| <direct name="out_3" input="RAMB36E1_512x72_sp.out[63:32]" output="RAMB36E1.DOBDO[31:0]"/> |
| <direct name="outp" input="RAMB36E1_512x72_sp.out[67:64]" output="RAMB36E1.DOPADOP[3:0]"/> |
| <direct name="outp_4" input="RAMB36E1_512x72_sp.out[71:68]" output="RAMB36E1.DOPBDOP[3:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_512x72_sp.clk[0]"/> |
| <complete name="clk_5" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_1024x36_REGB_sp"> |
| <pb_type name="RAMB36E1_1024x36_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="10" port_class="address"/> |
| <input name="data" num_pins="36" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="36" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_1024x36_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_1024x36_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_1024x36_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_1024x36_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB36E1.ADDRBWRADDRL[14:5]" output="RAMB36E1_1024x36_sp.addr"/> |
| <direct name="data" input="RAMB36E1.DIBDI[31:0]" output="RAMB36E1_1024x36_sp.data[31:0]"/> |
| <direct name="datap" input="RAMB36E1.DIPBDIP[3:0]" output="RAMB36E1_1024x36_sp.data[35:32]"/> |
| <direct name="we" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_1024x36_sp.we"/> |
| <direct name="out" input="RAMB36E1_1024x36_sp.out[31:0]" output="DOB_REG[31:0].D"/> |
| <direct name="outp" input="RAMB36E1_1024x36_sp.out[35:32]" output="DOB_REG[35:32].D"/> |
| <direct name="out_0" input="DOB_REG[31:0].Q" output="RAMB36E1.DOBDO[31:0]"/> |
| <direct name="outp_1" input="DOB_REG[35:32].Q" output="RAMB36E1.DOPBDOP[3:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_1024x36_sp.clk[0]"/> |
| <complete name="clk_2" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_1024x36_COMB_sp"> |
| <pb_type name="RAMB36E1_1024x36_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="10" port_class="address"/> |
| <input name="data" num_pins="36" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="36" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_1024x36_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_1024x36_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_1024x36_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_1024x36_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB36E1.ADDRBWRADDRL[14:5]" output="RAMB36E1_1024x36_sp.addr"/> |
| <direct name="data" input="RAMB36E1.DIBDI[31:0]" output="RAMB36E1_1024x36_sp.data[31:0]"/> |
| <direct name="datap" input="RAMB36E1.DIPBDIP[3:0]" output="RAMB36E1_1024x36_sp.data[35:32]"/> |
| <direct name="we" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_1024x36_sp.we"/> |
| <direct name="out" input="RAMB36E1_1024x36_sp.out[31:0]" output="RAMB36E1.DOBDO[31:0]"/> |
| <direct name="outp" input="RAMB36E1_1024x36_sp.out[35:32]" output="RAMB36E1.DOPBDOP[3:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_1024x36_sp.clk[0]"/> |
| <complete name="clk_0" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_2048x18_REGB_sp"> |
| <pb_type name="RAMB36E1_2048x18_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="11" port_class="address"/> |
| <input name="data" num_pins="18" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="18" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_2048x18_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_2048x18_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_2048x18_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_2048x18_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB36E1.ADDRBWRADDRL[14:4]" output="RAMB36E1_2048x18_sp.addr"/> |
| <direct name="data" input="RAMB36E1.DIBDI[15:0]" output="RAMB36E1_2048x18_sp.data[15:0]"/> |
| <direct name="data_0" input="RAMB36E1.DIPBDIP[1:0]" output="RAMB36E1_2048x18_sp.data[17:16]"/> |
| <direct name="we" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_2048x18_sp.we"/> |
| <direct name="out" input="RAMB36E1_2048x18_sp.out[15:0]" output="DOB_REG[15:0].D"/> |
| <direct name="outp" input="RAMB36E1_2048x18_sp.out[17:16]" output="DOB_REG[17:16].D"/> |
| <direct name="out_1" input="DOB_REG[15:0].Q" output="RAMB36E1.DOBDO[15:0]"/> |
| <direct name="outp_2" input="DOB_REG[17:16].Q" output="RAMB36E1.DOPBDOP[1:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_2048x18_sp.clk[0]"/> |
| <complete name="clk_3" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_2048x18_COMB_sp"> |
| <pb_type name="RAMB36E1_2048x18_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="11" port_class="address"/> |
| <input name="data" num_pins="18" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="18" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_2048x18_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_2048x18_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_2048x18_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_2048x18_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB36E1.ADDRBWRADDRL[14:4]" output="RAMB36E1_2048x18_sp.addr"/> |
| <direct name="data" input="RAMB36E1.DIBDI[15:0]" output="RAMB36E1_2048x18_sp.data[15:0]"/> |
| <direct name="data_0" input="RAMB36E1.DIPBDIP[1:0]" output="RAMB36E1_2048x18_sp.data[17:16]"/> |
| <direct name="we" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_2048x18_sp.we"/> |
| <direct name="out" input="RAMB36E1_2048x18_sp.out[15:0]" output="RAMB36E1.DOBDO[15:0]"/> |
| <direct name="outp" input="RAMB36E1_2048x18_sp.out[17:16]" output="RAMB36E1.DOPBDOP[1:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_2048x18_sp.clk[0]"/> |
| <complete name="clk_1" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_4096x9_REGB_sp"> |
| <pb_type name="RAMB36E1_4096x9_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="12" port_class="address"/> |
| <input name="data" num_pins="9" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="9" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_4096x9_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_4096x9_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_4096x9_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_4096x9_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB36E1.ADDRARDADDRL[14:3]" output="RAMB36E1_4096x9_sp.addr"/> |
| <direct name="data" input="RAMB36E1.DIBDI[7:0]" output="RAMB36E1_4096x9_sp.data[7:0]"/> |
| <direct name="data_0" input="RAMB36E1.DIPBDIP[0]" output="RAMB36E1_4096x9_sp.data[8]"/> |
| <direct name="we" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_4096x9_sp.we"/> |
| <direct name="out" input="RAMB36E1_4096x9_sp.out[7:0]" output="DOB_REG[7:0].D"/> |
| <direct name="outp" input="RAMB36E1_4096x9_sp.out[8]" output="DOB_REG[8].D"/> |
| <direct name="out_1" input="DOB_REG[7:0].Q" output="RAMB36E1.DOBDO[7:0]"/> |
| <direct name="outp_2" input="DOB_REG[8].Q" output="RAMB36E1.DOPBDOP[0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_4096x9_sp.clk[0]"/> |
| <complete name="clk_3" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_4096x9_COMB_sp"> |
| <pb_type name="RAMB36E1_4096x9_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="12" port_class="address"/> |
| <input name="data" num_pins="9" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="9" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_4096x9_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_4096x9_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_4096x9_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_4096x9_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB36E1.ADDRARDADDRL[14:3]" output="RAMB36E1_4096x9_sp.addr"/> |
| <direct name="data" input="RAMB36E1.DIBDI[7:0]" output="RAMB36E1_4096x9_sp.data[7:0]"/> |
| <direct name="data_0" input="RAMB36E1.DIPBDIP[0]" output="RAMB36E1_4096x9_sp.data[8]"/> |
| <direct name="we" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_4096x9_sp.we"/> |
| <direct name="out" input="RAMB36E1_4096x9_sp.out[7:0]" output="RAMB36E1.DOBDO[7:0]"/> |
| <direct name="outp" input="RAMB36E1_4096x9_sp.out[8]" output="RAMB36E1.DOPBDOP[0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_4096x9_sp.clk[0]"/> |
| <complete name="clk_1" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_8192x4_REGB_sp"> |
| <pb_type name="RAMB36E1_8192x4_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="13" port_class="address"/> |
| <input name="data" num_pins="4" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="4" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_8192x4_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_8192x4_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_8192x4_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_8192x4_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB36E1.ADDRBWRADDRL[14:2]" output="RAMB36E1_8192x4_sp.addr"/> |
| <direct name="data" input="RAMB36E1.DIBDI[3:0]" output="RAMB36E1_8192x4_sp.data[3:0]"/> |
| <direct name="we" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_8192x4_sp.we"/> |
| <direct name="out" input="RAMB36E1_8192x4_sp.out[3:0]" output="DOB_REG[3:0].D"/> |
| <direct name="out_0" input="DOB_REG[3:0].Q" output="RAMB36E1.DOBDO[3:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_8192x4_sp.clk[0]"/> |
| <complete name="clk_1" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_8192x4_COMB_sp"> |
| <pb_type name="RAMB36E1_8192x4_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="13" port_class="address"/> |
| <input name="data" num_pins="4" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="4" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_8192x4_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_8192x4_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_8192x4_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_8192x4_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB36E1.ADDRBWRADDRL[14:2]" output="RAMB36E1_8192x4_sp.addr"/> |
| <direct name="data" input="RAMB36E1.DIBDI[3:0]" output="RAMB36E1_8192x4_sp.data[3:0]"/> |
| <direct name="we" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_8192x4_sp.we"/> |
| <direct name="out" input="RAMB36E1_8192x4_sp.out[3:0]" output="RAMB36E1.DOBDO[3:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_8192x4_sp.clk[0]"/> |
| <complete name="clk_0" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_16384x2_REGB_sp"> |
| <pb_type name="RAMB36E1_16384x2_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="14" port_class="address"/> |
| <input name="data" num_pins="2" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="2" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_16384x2_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_16384x2_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_16384x2_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_16384x2_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB36E1.ADDRBWRADDRL[14:1]" output="RAMB36E1_16384x2_sp.addr"/> |
| <direct name="data" input="RAMB36E1.DIBDI[1:0]" output="RAMB36E1_16384x2_sp.data[1:0]"/> |
| <direct name="we" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_16384x2_sp.we"/> |
| <direct name="out" input="RAMB36E1_16384x2_sp.out[1:0]" output="DOB_REG[1:0].D"/> |
| <direct name="out_0" input="DOB_REG[1:0].Q" output="RAMB36E1.DOBDO[1:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_16384x2_sp.clk[0]"/> |
| <complete name="clk_1" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_16384x2_COMB_sp"> |
| <pb_type name="RAMB36E1_16384x2_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="14" port_class="address"/> |
| <input name="data" num_pins="2" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="2" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_16384x2_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_16384x2_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_16384x2_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_16384x2_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB36E1.ADDRBWRADDRL[14:1]" output="RAMB36E1_16384x2_sp.addr"/> |
| <direct name="data" input="RAMB36E1.DIBDI[1:0]" output="RAMB36E1_16384x2_sp.data[1:0]"/> |
| <direct name="we" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_16384x2_sp.we"/> |
| <direct name="out" input="RAMB36E1_16384x2_sp.out[1:0]" output="RAMB36E1.DOBDO[1:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_16384x2_sp.clk[0]"/> |
| <complete name="clk_0" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_32768x1_REGB_sp"> |
| <pb_type name="RAMB36E1_32768x1_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="15" port_class="address"/> |
| <input name="data" num_pins="1" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="1" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_32768x1_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_32768x1_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_32768x1_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_32768x1_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB36E1.ADDRBWRADDRL[14:0]" output="RAMB36E1_32768x1_sp.addr"/> |
| <direct name="data" input="RAMB36E1.DIBDI[0]" output="RAMB36E1_32768x1_sp.data"/> |
| <direct name="we" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_32768x1_sp.we"/> |
| <direct name="out" input="RAMB36E1_32768x1_sp.out" output="DOB_REG[0].D"> |
| <!--pack_pattern name="RAMB36E1_32768x1[ 0:0]_DOB" in_port="RAMB36E1_32768x1_sp.out[ 0:0]" out_port="DOB_REG[ 0:0].D"/--> |
| </direct> |
| <direct name="out_0" input="DOB_REG[0].Q" output="RAMB36E1.DOBDO[0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_32768x1_sp.clk[0]"/> |
| <complete name="clk_1" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_32768x1_COMB_sp"> |
| <pb_type name="RAMB36E1_32768x1_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1"> |
| <input name="addr" num_pins="15" port_class="address"/> |
| <input name="data" num_pins="1" port_class="data_in"/> |
| <input name="we" num_pins="1" port_class="write_en"/> |
| <output name="out" num_pins="1" port_class="data_out"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_32768x1_sp.addr" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_32768x1_sp.data" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_32768x1_sp.we" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_32768x1_sp.out" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr" input="RAMB36E1.ADDRBWRADDRL[14:0]" output="RAMB36E1_32768x1_sp.addr"/> |
| <direct name="data" input="RAMB36E1.DIBDI[0]" output="RAMB36E1_32768x1_sp.data"/> |
| <direct name="we" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_32768x1_sp.we"/> |
| <direct name="out" input="RAMB36E1_32768x1_sp.out" output="RAMB36E1.DOBDO[0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_32768x1_sp.clk[0]"/> |
| <complete name="clk_0" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <!-- RAMB36E1 Dual-port RAM --> |
| <mode name="RAMB36E1_1024x36_REGAB_dp"> |
| <pb_type name="RAMB36E1_1024x36_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="10" port_class="addr1"/> |
| <input name="addr2" num_pins="10" port_class="addr2"/> |
| <input name="data1" num_pins="36" port_class="data_in1"/> |
| <input name="data2" num_pins="36" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="36" port_class="data_out1"/> |
| <output name="out2" num_pins="36" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_1024x36_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_1024x36_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_1024x36_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_1024x36_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_1024x36_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_1024x36_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_1024x36_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_1024x36_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:5]" output="RAMB36E1_1024x36_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[31:0]" output="RAMB36E1_1024x36_dp.data1[31:0]"/> |
| <direct name="data1_0" input="RAMB36E1.DIPADIP[3:0]" output="RAMB36E1_1024x36_dp.data1[35:32]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_1024x36_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_1024x36_dp.out1" output="DOA_REG[35:0].D"/> |
| <direct name="out1_1" input="DOA_REG[31:0].Q" output="RAMB36E1.DOADO[31:0]"/> |
| <direct name="out1p" input="DOA_REG[35:32].Q" output="RAMB36E1.DOPADOP[3:0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:5]" output="RAMB36E1_1024x36_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[31:0]" output="DOB_REG[31:0].D"/> |
| <direct name="data2_2" input="RAMB36E1.DIPBDIP[3:0]" output="DOB_REG[35:32].D"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_1024x36_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_1024x36_dp.out2" output="DOB_REG[35:0].D"/> |
| <direct name="out2_3" input="DOB_REG[31:0].Q" output="RAMB36E1.DOBDO[31:0]"/> |
| <direct name="out2p" input="DOB_REG[35:32].Q" output="RAMB36E1.DOPBDOP[3:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_1024x36_dp.clk[0]"/> |
| <complete name="clk_4" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_1024x36_REGA_dp"> |
| <pb_type name="RAMB36E1_1024x36_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="10" port_class="addr1"/> |
| <input name="addr2" num_pins="10" port_class="addr2"/> |
| <input name="data1" num_pins="36" port_class="data_in1"/> |
| <input name="data2" num_pins="36" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="36" port_class="data_out1"/> |
| <output name="out2" num_pins="36" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_1024x36_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_1024x36_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_1024x36_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_1024x36_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_1024x36_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_1024x36_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_1024x36_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_1024x36_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:5]" output="RAMB36E1_1024x36_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[31:0]" output="RAMB36E1_1024x36_dp.data1[31:0]"/> |
| <direct name="data1_0" input="RAMB36E1.DIPADIP[3:0]" output="RAMB36E1_1024x36_dp.data1[35:32]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_1024x36_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_1024x36_dp.out1" output="DOA_REG[35:0].D"/> |
| <direct name="out1_1" input="DOA_REG[31:0].Q" output="RAMB36E1.DOADO[31:0]"/> |
| <direct name="out1p" input="DOA_REG[35:32].Q" output="RAMB36E1.DOPADOP[3:0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:5]" output="RAMB36E1_1024x36_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[31:0]" output="RAMB36E1_1024x36_dp.data2[31:0]"/> |
| <direct name="data2_2" input="RAMB36E1.DIPBDIP[3:0]" output="RAMB36E1_1024x36_dp.data2[35:32]"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_1024x36_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_1024x36_dp.out2[31:0]" output="RAMB36E1.DOBDO[31:0]"/> |
| <direct name="out2p" input="RAMB36E1_1024x36_dp.out2[35:32]" output="RAMB36E1.DOPBDOP[3:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_1024x36_dp.clk[0]"/> |
| <complete name="clk_3" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_1024x36_REGB_dp"> |
| <pb_type name="RAMB36E1_1024x36_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="10" port_class="addr1"/> |
| <input name="addr2" num_pins="10" port_class="addr2"/> |
| <input name="data1" num_pins="36" port_class="data_in1"/> |
| <input name="data2" num_pins="36" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="36" port_class="data_out1"/> |
| <output name="out2" num_pins="36" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_1024x36_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_1024x36_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_1024x36_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_1024x36_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_1024x36_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_1024x36_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_1024x36_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_1024x36_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:5]" output="RAMB36E1_1024x36_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[31:0]" output="RAMB36E1_1024x36_dp.data1[31:0]"/> |
| <direct name="data1_0" input="RAMB36E1.DIPADIP[3:0]" output="RAMB36E1_1024x36_dp.data1[35:32]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_1024x36_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_1024x36_dp.out1[31:0]" output="RAMB36E1.DOADO[31:0]"/> |
| <direct name="out1p" input="RAMB36E1_1024x36_dp.out1[35:32]" output="RAMB36E1.DOPADOP[3:0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:5]" output="RAMB36E1_1024x36_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[31:0]" output="RAMB36E1_1024x36_dp.data2[31:0]"/> |
| <direct name="data2_1" input="RAMB36E1.DIPBDIP[3:0]" output="RAMB36E1_1024x36_dp.data2[35:32]"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_1024x36_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_1024x36_dp.out2" output="DOB_REG[35:0].D"/> |
| <direct name="out2_2" input="DOB_REG[31:0].Q" output="RAMB36E1.DOBDO[31:0]"/> |
| <direct name="out2p" input="DOB_REG[35:32].Q" output="RAMB36E1.DOPBDOP[3:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_1024x36_dp.clk[0]"/> |
| <complete name="clk_3" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_1024x36_COMB_dp"> |
| <pb_type name="RAMB36E1_1024x36_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="10" port_class="addr1"/> |
| <input name="addr2" num_pins="10" port_class="addr2"/> |
| <input name="data1" num_pins="36" port_class="data_in1"/> |
| <input name="data2" num_pins="36" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="36" port_class="data_out1"/> |
| <output name="out2" num_pins="36" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_1024x36_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_1024x36_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_1024x36_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_1024x36_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_1024x36_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_1024x36_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_1024x36_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_1024x36_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:5]" output="RAMB36E1_1024x36_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[31:0]" output="RAMB36E1_1024x36_dp.data1[31:0]"/> |
| <direct name="data1_0" input="RAMB36E1.DIPADIP[3:0]" output="RAMB36E1_1024x36_dp.data1[35:32]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_1024x36_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_1024x36_dp.out1[31:0]" output="RAMB36E1.DOADO[31:0]"/> |
| <direct name="out1p" input="RAMB36E1_1024x36_dp.out1[35:32]" output="RAMB36E1.DOPADOP[3:0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:5]" output="RAMB36E1_1024x36_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[31:0]" output="RAMB36E1_1024x36_dp.data2[31:0]"/> |
| <direct name="data2_1" input="RAMB36E1.DIPBDIP[3:0]" output="RAMB36E1_1024x36_dp.data2[35:32]"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_1024x36_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_1024x36_dp.out2[31:0]" output="RAMB36E1.DOBDO[31:0]"/> |
| <direct name="out2p" input="RAMB36E1_1024x36_dp.out2[35:32]" output="RAMB36E1.DOPBDOP[3:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_1024x36_dp.clk[0]"/> |
| <complete name="clk_2" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_2048x18_REGAB_dp"> |
| <pb_type name="RAMB36E1_2048x18_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="11" port_class="addr1"/> |
| <input name="addr2" num_pins="11" port_class="addr2"/> |
| <input name="data1" num_pins="18" port_class="data_in1"/> |
| <input name="data2" num_pins="18" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="18" port_class="data_out1"/> |
| <output name="out2" num_pins="18" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_2048x18_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_2048x18_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_2048x18_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_2048x18_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_2048x18_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_2048x18_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_2048x18_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_2048x18_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:4]" output="RAMB36E1_2048x18_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[15:0]" output="RAMB36E1_2048x18_dp.data1[15:0]"/> |
| <direct name="data1_0" input="RAMB36E1.DIPADIP[1:0]" output="RAMB36E1_2048x18_dp.data1[17:16]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_2048x18_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_2048x18_dp.out1" output="DOA_REG[17:0].D"/> |
| <direct name="out1_1" input="DOA_REG[15:0].Q" output="RAMB36E1.DOADO[15:0]"/> |
| <direct name="out1p" input="DOA_REG[17:16].Q" output="RAMB36E1.DOPADOP[1:0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:4]" output="RAMB36E1_2048x18_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[15:0]" output="RAMB36E1_2048x18_dp.data2[15:0]"/> |
| <direct name="data2_2" input="RAMB36E1.DIPBDIP[1:0]" output="RAMB36E1_2048x18_dp.data2[17:16]"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_2048x18_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_2048x18_dp.out2" output="DOB_REG[17:0].D"/> |
| <direct name="out2_3" input="DOB_REG[15:0].Q" output="RAMB36E1.DOBDO[15:0]"/> |
| <direct name="out2p" input="DOB_REG[17:16].Q" output="RAMB36E1.DOPBDOP[1:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_2048x18_dp.clk[0]"/> |
| <complete name="clk_4" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_2048x18_REGA_dp"> |
| <pb_type name="RAMB36E1_2048x18_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="11" port_class="addr1"/> |
| <input name="addr2" num_pins="11" port_class="addr2"/> |
| <input name="data1" num_pins="18" port_class="data_in1"/> |
| <input name="data2" num_pins="18" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="18" port_class="data_out1"/> |
| <output name="out2" num_pins="18" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_2048x18_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_2048x18_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_2048x18_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_2048x18_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_2048x18_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_2048x18_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_2048x18_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_2048x18_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:4]" output="RAMB36E1_2048x18_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[15:0]" output="RAMB36E1_2048x18_dp.data1[15:0]"/> |
| <direct name="data1_0" input="RAMB36E1.DIPADIP[1:0]" output="RAMB36E1_2048x18_dp.data1[17:16]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_2048x18_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_2048x18_dp.out1" output="DOA_REG[17:0].D"/> |
| <direct name="out1_1" input="DOA_REG[15:0].Q" output="RAMB36E1.DOADO[15:0]"/> |
| <direct name="out1p" input="DOA_REG[17:16].Q" output="RAMB36E1.DOPADOP[1:0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:4]" output="RAMB36E1_2048x18_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[15:0]" output="RAMB36E1_2048x18_dp.data2[15:0]"/> |
| <direct name="data2_2" input="RAMB36E1.DIPBDIP[1:0]" output="RAMB36E1_2048x18_dp.data2[17:16]"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_2048x18_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_2048x18_dp.out2[15:0]" output="RAMB36E1.DOBDO[15:0]"/> |
| <direct name="out2p" input="RAMB36E1_2048x18_dp.out2[17:16]" output="RAMB36E1.DOPBDOP[1:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_2048x18_dp.clk[0]"/> |
| <complete name="clk_3" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_2048x18_REGB_dp"> |
| <pb_type name="RAMB36E1_2048x18_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="11" port_class="addr1"/> |
| <input name="addr2" num_pins="11" port_class="addr2"/> |
| <input name="data1" num_pins="18" port_class="data_in1"/> |
| <input name="data2" num_pins="18" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="18" port_class="data_out1"/> |
| <output name="out2" num_pins="18" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_2048x18_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_2048x18_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_2048x18_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_2048x18_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_2048x18_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_2048x18_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_2048x18_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_2048x18_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:4]" output="RAMB36E1_2048x18_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[15:0]" output="RAMB36E1_2048x18_dp.data1[15:0]"/> |
| <direct name="data1p" input="RAMB36E1.DIPADIP[1:0]" output="RAMB36E1_2048x18_dp.data1[17:16]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_2048x18_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_2048x18_dp.out1[15:0]" output="RAMB36E1.DOADO[15:0]"/> |
| <direct name="out1p" input="RAMB36E1_2048x18_dp.out1[17:16]" output="RAMB36E1.DOPADOP[1:0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:4]" output="RAMB36E1_2048x18_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[15:0]" output="RAMB36E1_2048x18_dp.data2[15:0]"/> |
| <direct name="data2p" input="RAMB36E1.DIPBDIP[1:0]" output="RAMB36E1_2048x18_dp.data2[17:16]"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_2048x18_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_2048x18_dp.out2" output="DOB_REG[17:0].D"/> |
| <direct name="out2_0" input="DOB_REG[15:0].Q" output="RAMB36E1.DOBDO[15:0]"/> |
| <direct name="out2p" input="DOB_REG[17:16].Q" output="RAMB36E1.DOPBDOP[1:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_2048x18_dp.clk[0]"/> |
| <complete name="clk_1" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_2048x18_COMB_dp"> |
| <pb_type name="RAMB36E1_2048x18_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="11" port_class="addr1"/> |
| <input name="addr2" num_pins="11" port_class="addr2"/> |
| <input name="data1" num_pins="18" port_class="data_in1"/> |
| <input name="data2" num_pins="18" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="18" port_class="data_out1"/> |
| <output name="out2" num_pins="18" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_2048x18_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_2048x18_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_2048x18_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_2048x18_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_2048x18_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_2048x18_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_2048x18_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_2048x18_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:4]" output="RAMB36E1_2048x18_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[15:0]" output="RAMB36E1_2048x18_dp.data1[15:0]"/> |
| <direct name="data1_0" input="RAMB36E1.DIPADIP[1:0]" output="RAMB36E1_2048x18_dp.data1[1:0]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_2048x18_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_2048x18_dp.out1[15:0]" output="RAMB36E1.DOADO[15:0]"/> |
| <direct name="out1p" input="RAMB36E1_2048x18_dp.out1[17:16]" output="RAMB36E1.DOPADOP[1:0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:4]" output="RAMB36E1_2048x18_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[15:0]" output="RAMB36E1_2048x18_dp.data2[15:0]"/> |
| <direct name="data2_1" input="RAMB36E1.DIPBDIP[1:0]" output="RAMB36E1_2048x18_dp.data2[17:16]"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_2048x18_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_2048x18_dp.out2[15:0]" output="RAMB36E1.DOBDO[15:0]"/> |
| <direct name="out2p" input="RAMB36E1_2048x18_dp.out2[17:16]" output="RAMB36E1.DOPBDOP[1:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_2048x18_dp.clk[0]"/> |
| <complete name="clk_2" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_4096x9_REGAB_dp"> |
| <pb_type name="RAMB36E1_4096x9_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="12" port_class="addr1"/> |
| <input name="addr2" num_pins="12" port_class="addr2"/> |
| <input name="data1" num_pins="9" port_class="data_in1"/> |
| <input name="data2" num_pins="9" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="9" port_class="data_out1"/> |
| <output name="out2" num_pins="9" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_4096x9_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_4096x9_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_4096x9_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_4096x9_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_4096x9_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_4096x9_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_4096x9_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_4096x9_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:3]" output="RAMB36E1_4096x9_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[7:0]" output="RAMB36E1_4096x9_dp.data1[7:0]"/> |
| <direct name="data1_0" input="RAMB36E1.DIPADIP[0]" output="RAMB36E1_4096x9_dp.data1[8]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_4096x9_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_4096x9_dp.out1" output="DOA_REG[8:0].D"/> |
| <direct name="out1_1" input="DOA_REG[7:0].Q" output="RAMB36E1.DOADO[7:0]"/> |
| <direct name="out1p" input="DOA_REG[8].Q" output="RAMB36E1.DOPADOP[0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:3]" output="RAMB36E1_4096x9_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[7:0]" output="RAMB36E1_4096x9_dp.data2[7:0]"/> |
| <direct name="data2_2" input="RAMB36E1.DIPBDIP[0]" output="RAMB36E1_4096x9_dp.data2[8]"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_4096x9_dp.we2"/> |
| <direct name="out1_3" input="RAMB36E1_4096x9_dp.out2" output="DOB_REG[8:0].D"/> |
| <direct name="out2" input="DOB_REG[7:0].Q" output="RAMB36E1.DOBDO[7:0]"/> |
| <direct name="out2p" input="DOB_REG[8].Q" output="RAMB36E1.DOPBDOP[0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_4096x9_dp.clk[0]"/> |
| <complete name="clk_4" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_4096x9_REGA_dp"> |
| <pb_type name="RAMB36E1_4096x9_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="12" port_class="addr1"/> |
| <input name="addr2" num_pins="12" port_class="addr2"/> |
| <input name="data1" num_pins="9" port_class="data_in1"/> |
| <input name="data2" num_pins="9" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="9" port_class="data_out1"/> |
| <output name="out2" num_pins="9" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_4096x9_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_4096x9_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_4096x9_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_4096x9_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_4096x9_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_4096x9_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_4096x9_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_4096x9_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:3]" output="RAMB36E1_4096x9_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[7:0]" output="RAMB36E1_4096x9_dp.data1[7:0]"/> |
| <direct name="data1_0" input="RAMB36E1.DIPADIP[0]" output="RAMB36E1_4096x9_dp.data1[8]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_4096x9_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_4096x9_dp.out1[7:0]" output="DOA_REG[7:0].D"/> |
| <direct name="out1p" input="RAMB36E1_4096x9_dp.out1[8]" output="DOA_REG[8].D"/> |
| <direct name="out1_1" input="DOA_REG[7:0].Q" output="RAMB36E1.DOADO[7:0]"/> |
| <direct name="out1p_2" input="DOA_REG[8].Q" output="RAMB36E1.DOPADOP[0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:3]" output="RAMB36E1_4096x9_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[7:0]" output="RAMB36E1_4096x9_dp.data2[7:0]"/> |
| <direct name="data2_3" input="RAMB36E1.DIPBDIP[0]" output="RAMB36E1_4096x9_dp.data2[8]"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_4096x9_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_4096x9_dp.out2[7:0]" output="RAMB36E1.DOBDO[7:0]"/> |
| <direct name="out2p" input="RAMB36E1_4096x9_dp.out2[8]" output="RAMB36E1.DOPBDOP[0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_4096x9_dp.clk[0]"/> |
| <complete name="clk_4" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_4096x9_REGB_dp"> |
| <pb_type name="RAMB36E1_4096x9_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="12" port_class="addr1"/> |
| <input name="addr2" num_pins="12" port_class="addr2"/> |
| <input name="data1" num_pins="9" port_class="data_in1"/> |
| <input name="data2" num_pins="9" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="9" port_class="data_out1"/> |
| <output name="out2" num_pins="9" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_4096x9_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_4096x9_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_4096x9_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_4096x9_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_4096x9_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_4096x9_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_4096x9_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_4096x9_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:3]" output="RAMB36E1_4096x9_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[7:0]" output="RAMB36E1_4096x9_dp.data1[7:0]"/> |
| <direct name="data1_0" input="RAMB36E1.DIPADIP[0]" output="RAMB36E1_4096x9_dp.data1[8]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_4096x9_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_4096x9_dp.out1[7:0]" output="RAMB36E1.DOADO[7:0]"/> |
| <direct name="out1p" input="RAMB36E1_4096x9_dp.out1[8]" output="RAMB36E1.DOPADOP[0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:3]" output="RAMB36E1_4096x9_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[7:0]" output="RAMB36E1_4096x9_dp.data2[7:0]"/> |
| <direct name="data2_1" input="RAMB36E1.DIPBDIP[0]" output="RAMB36E1_4096x9_dp.data2[8]"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_4096x9_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_4096x9_dp.out2[7:0]" output="DOB_REG[7:0].D"/> |
| <direct name="out2p" input="RAMB36E1_4096x9_dp.out2[8]" output="DOB_REG[8].D"/> |
| <direct name="out2_2" input="DOB_REG[7:0].Q" output="RAMB36E1.DOBDO[7:0]"/> |
| <direct name="out2p_3" input="DOB_REG[8].Q" output="RAMB36E1.DOPBDOP[0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_4096x9_dp.clk[0]"/> |
| <complete name="clk_4" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_4096x9_COMB_dp"> |
| <pb_type name="RAMB36E1_4096x9_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="12" port_class="addr1"/> |
| <input name="addr2" num_pins="12" port_class="addr2"/> |
| <input name="data1" num_pins="9" port_class="data_in1"/> |
| <input name="data2" num_pins="9" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="9" port_class="data_out1"/> |
| <output name="out2" num_pins="9" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_4096x9_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_4096x9_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_4096x9_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_4096x9_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_4096x9_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_4096x9_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_4096x9_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_4096x9_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:3]" output="RAMB36E1_4096x9_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[7:0]" output="RAMB36E1_4096x9_dp.data1[7:0]"/> |
| <direct name="data1_0" input="RAMB36E1.DIPADIP[0]" output="RAMB36E1_4096x9_dp.data1[8]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_4096x9_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_4096x9_dp.out1[7:0]" output="RAMB36E1.DOADO[7:0]"/> |
| <direct name="out1p" input="RAMB36E1_4096x9_dp.out1[8]" output="RAMB36E1.DOPADOP[0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:3]" output="RAMB36E1_4096x9_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[7:0]" output="RAMB36E1_4096x9_dp.data2[7:0]"/> |
| <direct name="data2_1" input="RAMB36E1.DIPBDIP[0]" output="RAMB36E1_4096x9_dp.data2[8]"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_4096x9_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_4096x9_dp.out2[7:0]" output="RAMB36E1.DOBDO[7:0]"/> |
| <direct name="out2p" input="RAMB36E1_4096x9_dp.out2[8]" output="RAMB36E1.DOPBDOP[0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_4096x9_dp.clk[0]"/> |
| <complete name="clk_2" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_8192x4_REGAB_dp"> |
| <pb_type name="RAMB36E1_8192x4_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="13" port_class="addr1"/> |
| <input name="addr2" num_pins="13" port_class="addr2"/> |
| <input name="data1" num_pins="4" port_class="data_in1"/> |
| <input name="data2" num_pins="4" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="4" port_class="data_out1"/> |
| <output name="out2" num_pins="4" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_8192x4_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_8192x4_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_8192x4_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_8192x4_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_8192x4_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_8192x4_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_8192x4_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_8192x4_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:2]" output="RAMB36E1_8192x4_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[3:0]" output="RAMB36E1_8192x4_dp.data1[3:0]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_8192x4_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_8192x4_dp.out1[3:0]" output="DOA_REG[3:0].D"/> |
| <direct name="out1_0" input="DOA_REG[3:0].Q" output="RAMB36E1.DOADO[3:0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:2]" output="RAMB36E1_8192x4_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[3:0]" output="RAMB36E1_8192x4_dp.data2[3:0]"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_8192x4_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_8192x4_dp.out2[3:0]" output="DOB_REG[3:0].D"/> |
| <direct name="out2_1" input="DOB_REG[3:0].Q" output="RAMB36E1.DOBDO[3:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_8192x4_dp.clk[0]"/> |
| <complete name="clk_2" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_8192x4_REGA_dp"> |
| <pb_type name="RAMB36E1_8192x4_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="13" port_class="addr1"/> |
| <input name="addr2" num_pins="13" port_class="addr2"/> |
| <input name="data1" num_pins="4" port_class="data_in1"/> |
| <input name="data2" num_pins="4" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="4" port_class="data_out1"/> |
| <output name="out2" num_pins="4" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_8192x4_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_8192x4_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_8192x4_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_8192x4_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_8192x4_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_8192x4_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_8192x4_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_8192x4_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:2]" output="RAMB36E1_8192x4_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[3:0]" output="RAMB36E1_8192x4_dp.data1[3:0]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_8192x4_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_8192x4_dp.out1[3:0]" output="DOA_REG[3:0].D"/> |
| <direct name="out1_0" input="DOA_REG[3:0].Q" output="RAMB36E1.DOADO[3:0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:2]" output="RAMB36E1_8192x4_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[3:0]" output="RAMB36E1_8192x4_dp.data2[3:0]"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_8192x4_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_8192x4_dp.out2[3:0]" output="RAMB36E1.DOBDO[3:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_8192x4_dp.clk[0]"/> |
| <complete name="clk_1" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_8192x4_REGB_dp"> |
| <pb_type name="RAMB36E1_8192x4_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="13" port_class="addr1"/> |
| <input name="addr2" num_pins="13" port_class="addr2"/> |
| <input name="data1" num_pins="4" port_class="data_in1"/> |
| <input name="data2" num_pins="4" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="4" port_class="data_out1"/> |
| <output name="out2" num_pins="4" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_8192x4_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_8192x4_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_8192x4_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_8192x4_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_8192x4_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_8192x4_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_8192x4_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_8192x4_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:2]" output="RAMB36E1_8192x4_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[3:0]" output="RAMB36E1_8192x4_dp.data1[3:0]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_8192x4_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_8192x4_dp.out1[3:0]" output="RAMB36E1.DOADO[3:0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:2]" output="RAMB36E1_8192x4_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIADI[3:0]" output="RAMB36E1_8192x4_dp.data2[3:0]"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_8192x4_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_8192x4_dp.out2[3:0]" output="DOB_REG[3:0].D"/> |
| <direct name="out2_0" input="DOB_REG[3:0].Q" output="RAMB36E1.DOBDO[3:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_8192x4_dp.clk[0]"/> |
| <complete name="clk_1" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_8192x4_COMB_dp"> |
| <pb_type name="RAMB36E1_8192x4_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="13" port_class="addr1"/> |
| <input name="addr2" num_pins="13" port_class="addr2"/> |
| <input name="data1" num_pins="4" port_class="data_in1"/> |
| <input name="data2" num_pins="4" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="4" port_class="data_out1"/> |
| <output name="out2" num_pins="4" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_8192x4_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_8192x4_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_8192x4_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_8192x4_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_8192x4_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_8192x4_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_8192x4_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_8192x4_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="4" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="4" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:2]" output="RAMB36E1_8192x4_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[3:0]" output="RAMB36E1_8192x4_dp.data1[3:0]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_8192x4_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_8192x4_dp.out1[3:0]" output="RAMB36E1.DOADO[3:0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:2]" output="RAMB36E1_8192x4_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIADI[3:0]" output="RAMB36E1_8192x4_dp.data2[3:0]"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_8192x4_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_8192x4_dp.out2[3:0]" output="RAMB36E1.DOBDO[3:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_8192x4_dp.clk[0]"/> |
| <complete name="clk_0" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_16384x2_REGAB_dp"> |
| <pb_type name="RAMB36E1_16384x2_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="14" port_class="addr1"/> |
| <input name="addr2" num_pins="14" port_class="addr2"/> |
| <input name="data1" num_pins="2" port_class="data_in1"/> |
| <input name="data2" num_pins="2" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="2" port_class="data_out1"/> |
| <output name="out2" num_pins="2" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_16384x2_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_16384x2_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_16384x2_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_16384x2_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_16384x2_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_16384x2_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_16384x2_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_16384x2_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:1]" output="RAMB36E1_16384x2_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[1:0]" output="RAMB36E1_16384x2_dp.data1[1:0]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_16384x2_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_16384x2_dp.out1[1:0]" output="DOA_REG[1:0].D"/> |
| <direct name="out1_0" input="DOA_REG[1:0].Q" output="RAMB36E1.DOADO[1:0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:1]" output="RAMB36E1_16384x2_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[1:0]" output="RAMB36E1_16384x2_dp.data2[1:0]"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_16384x2_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_16384x2_dp.out2[1:0]" output="DOB_REG[1:0].D"/> |
| <direct name="out2_1" input="DOB_REG[1:0].Q" output="RAMB36E1.DOBDO[1:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_16384x2_dp.clk[0]"/> |
| <complete name="clk_2" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_16384x2_REGA_dp"> |
| <pb_type name="RAMB36E1_16384x2_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="14" port_class="addr1"/> |
| <input name="addr2" num_pins="14" port_class="addr2"/> |
| <input name="data1" num_pins="2" port_class="data_in1"/> |
| <input name="data2" num_pins="2" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="2" port_class="data_out1"/> |
| <output name="out2" num_pins="2" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_16384x2_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_16384x2_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_16384x2_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_16384x2_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_16384x2_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_16384x2_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_16384x2_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_16384x2_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:1]" output="RAMB36E1_16384x2_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[1:0]" output="RAMB36E1_16384x2_dp.data1[1:0]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_16384x2_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_16384x2_dp.out1[1:0]" output="DOA_REG[1:0].D"/> |
| <direct name="out1_0" input="DOA_REG[1:0].Q" output="RAMB36E1.DOADO[1:0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:1]" output="RAMB36E1_16384x2_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[1:0]" output="RAMB36E1_16384x2_dp.data2[1:0]"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_16384x2_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_16384x2_dp.out2[1:0]" output="RAMB36E1.DOBDO[1:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_16384x2_dp.clk[0]"/> |
| <complete name="clk_1" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_16384x2_REGB_dp"> |
| <pb_type name="RAMB36E1_16384x2_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="14" port_class="addr1"/> |
| <input name="addr2" num_pins="14" port_class="addr2"/> |
| <input name="data1" num_pins="2" port_class="data_in1"/> |
| <input name="data2" num_pins="2" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="2" port_class="data_out1"/> |
| <output name="out2" num_pins="2" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_16384x2_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_16384x2_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_16384x2_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_16384x2_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_16384x2_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_16384x2_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_16384x2_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_16384x2_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:1]" output="RAMB36E1_16384x2_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[1:0]" output="RAMB36E1_16384x2_dp.data1[1:0]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_16384x2_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_16384x2_dp.out1[1:0]" output="RAMB36E1.DOADO[1:0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:1]" output="RAMB36E1_16384x2_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[1:0]" output="RAMB36E1_16384x2_dp.data2[1:0]"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_16384x2_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_16384x2_dp.out2[1:0]" output="DOB_REG[1:0].D"/> |
| <direct name="out2_0" input="DOB_REG[1:0].Q" output="RAMB36E1.DOBDO[1:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_16384x2_dp.clk[0]"/> |
| <complete name="clk_1" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_16384x2_COMB_dp"> |
| <pb_type name="RAMB36E1_16384x2_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="14" port_class="addr1"/> |
| <input name="addr2" num_pins="14" port_class="addr2"/> |
| <input name="data1" num_pins="2" port_class="data_in1"/> |
| <input name="data2" num_pins="2" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="2" port_class="data_out1"/> |
| <output name="out2" num_pins="2" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_16384x2_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_16384x2_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_16384x2_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_16384x2_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_16384x2_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_16384x2_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_16384x2_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_16384x2_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:1]" output="RAMB36E1_16384x2_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[1:0]" output="RAMB36E1_16384x2_dp.data1[1:0]"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_16384x2_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_16384x2_dp.out1[1:0]" output="RAMB36E1.DOADO[1:0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:1]" output="RAMB36E1_16384x2_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[1:0]" output="RAMB36E1_16384x2_dp.data2[1:0]"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_16384x2_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_16384x2_dp.out2[1:0]" output="RAMB36E1.DOBDO[1:0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_16384x2_dp.clk[0]"/> |
| <complete name="clk_0" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_32768x1_REGAB_dp"> |
| <pb_type name="RAMB36E1_32768x1_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="15" port_class="addr1"/> |
| <input name="addr2" num_pins="15" port_class="addr2"/> |
| <input name="data1" num_pins="1" port_class="data_in1"/> |
| <input name="data2" num_pins="1" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="1" port_class="data_out1"/> |
| <output name="out2" num_pins="1" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_32768x1_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_32768x1_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_32768x1_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_32768x1_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_32768x1_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_32768x1_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_32768x1_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_32768x1_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:0]" output="RAMB36E1_32768x1_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[0]" output="RAMB36E1_32768x1_dp.data1"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_32768x1_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_32768x1_dp.out1" output="DOA_REG[0].D"/> |
| <direct name="out1_0" input="DOA_REG[0].Q" output="RAMB36E1.DOADO[0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:0]" output="RAMB36E1_32768x1_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[0]" output="RAMB36E1_32768x1_dp.data2"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_32768x1_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_32768x1_dp.out2" output="DOB_REG[0].D"/> |
| <direct name="out2_1" input="DOB_REG[0].Q" output="RAMB36E1.DOBDO[0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_32768x1_dp.clk[0]"/> |
| <complete name="clk_2" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_32768x1_REGA_dp"> |
| <pb_type name="RAMB36E1_32768x1_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="15" port_class="addr1"/> |
| <input name="addr2" num_pins="15" port_class="addr2"/> |
| <input name="data1" num_pins="1" port_class="data_in1"/> |
| <input name="data2" num_pins="1" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="1" port_class="data_out1"/> |
| <output name="out2" num_pins="1" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_32768x1_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_32768x1_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_32768x1_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_32768x1_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_32768x1_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_32768x1_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_32768x1_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_32768x1_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:0]" output="RAMB36E1_32768x1_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[0]" output="RAMB36E1_32768x1_dp.data1"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_32768x1_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_32768x1_dp.out1" output="DOA_REG[0].D"/> |
| <direct name="out1_0" input="DOA_REG[0].Q" output="RAMB36E1.DOADO[0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:0]" output="RAMB36E1_32768x1_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[0]" output="RAMB36E1_32768x1_dp.data2"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_32768x1_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_32768x1_dp.out2" output="RAMB36E1.DOBDO[0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_32768x1_dp.clk[0]"/> |
| <complete name="clk_1" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_32768x1_REGB_dp"> |
| <pb_type name="RAMB36E1_32768x1_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="15" port_class="addr1"/> |
| <input name="addr2" num_pins="15" port_class="addr2"/> |
| <input name="data1" num_pins="1" port_class="data_in1"/> |
| <input name="data2" num_pins="1" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="1" port_class="data_out1"/> |
| <output name="out2" num_pins="1" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_32768x1_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_32768x1_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_32768x1_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_32768x1_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_32768x1_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_32768x1_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_32768x1_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_32768x1_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:0]" output="RAMB36E1_32768x1_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[0]" output="RAMB36E1_32768x1_dp.data1"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_32768x1_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_32768x1_dp.out1" output="RAMB36E1.DOADO[0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:0]" output="RAMB36E1_32768x1_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[0]" output="RAMB36E1_32768x1_dp.data2"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_32768x1_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_32768x1_dp.out2" output="DOB_REG[0].D"/> |
| <direct name="out2_0" input="DOB_REG[0].Q" output="RAMB36E1.DOBDO[0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_32768x1_dp.clk[0]"/> |
| <complete name="clk_1" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| <mode name="RAMB36E1_32768x1_COMB_dp"> |
| <pb_type name="RAMB36E1_32768x1_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> |
| <input name="addr1" num_pins="15" port_class="addr1"/> |
| <input name="addr2" num_pins="15" port_class="addr2"/> |
| <input name="data1" num_pins="1" port_class="data_in1"/> |
| <input name="data2" num_pins="1" port_class="data_in2"/> |
| <input name="we1" num_pins="1" port_class="write_en1"/> |
| <input name="we2" num_pins="1" port_class="write_en2"/> |
| <output name="out1" num_pins="1" port_class="data_out1"/> |
| <output name="out2" num_pins="1" port_class="data_out2"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_32768x1_dp.addr1" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_32768x1_dp.data1" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_32768x1_dp.we1" clock="clk"/> |
| <T_setup value="0.480e-9" port="RAMB36E1_32768x1_dp.addr2" clock="clk"/> |
| <T_setup value="0.707e-9" port="RAMB36E1_32768x1_dp.data2" clock="clk"/> |
| <T_setup value="0.515e-9" port="RAMB36E1_32768x1_dp.we2" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_32768x1_dp.out1" clock="clk"/> |
| <T_clock_to_Q max="2.073e-9" port="RAMB36E1_32768x1_dp.out2" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOA_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOA_REG.Q" clock="clk"/> |
| </pb_type> |
| <pb_type name="DOB_REG" blif_model=".latch" num_pb="36" class="flipflop"> |
| <input name="D" num_pins="1" port_class="D"/> |
| <output name="Q" num_pins="1" port_class="Q"/> |
| <clock name="clk" num_pins="1" port_class="clock"/> |
| <T_clock_to_Q max="0.54e-9" port="DOB_REG.Q" clock="clk"/> |
| </pb_type> |
| <interconnect> |
| <direct name="addr1" input="RAMB36E1.ADDRARDADDRL[14:0]" output="RAMB36E1_32768x1_dp.addr1"/> |
| <direct name="data1" input="RAMB36E1.DIADI[0]" output="RAMB36E1_32768x1_dp.data1"/> |
| <direct name="we1" input="RAMB36E1.WEAL[0]" output="RAMB36E1_32768x1_dp.we1"/> |
| <direct name="out1" input="RAMB36E1_32768x1_dp.out1" output="RAMB36E1.DOADO[0]"/> |
| <direct name="addr2" input="RAMB36E1.ADDRBWRADDRL[14:0]" output="RAMB36E1_32768x1_dp.addr2"/> |
| <direct name="data2" input="RAMB36E1.DIBDI[0]" output="RAMB36E1_32768x1_dp.data2"/> |
| <direct name="we2" input="RAMB36E1.WEBWEL[0]" output="RAMB36E1_32768x1_dp.we2"/> |
| <direct name="out2" input="RAMB36E1_32768x1_dp.out2" output="RAMB36E1.DOBDO[0]"/> |
| <direct name="clk" input="RAMB36E1.CLKARDCLKL" output="RAMB36E1_32768x1_dp.clk[0]"/> |
| <complete name="clk_0" input="RAMB36E1.CLKARDCLKL" output="DOA_REG.clk DOB_REG.clk"/> |
| </interconnect> |
| </mode> |
| </pb_type> |
| <pb_type name="BUFG"> |
| <input name="I" num_pins="2"/> |
| <input name="S" num_pins="2"/> |
| <input name="CE" num_pins="2"/> |
| <input name="IGNORE" num_pins="2"/> |
| <!-- 8 --> |
| <output name="O" num_pins="1"/> |
| <!-- 9 --> |
| <output name="GND_WIRE" num_pins="1"/> |
| <output name="VCC_WIRE" num_pins="1"/> |
| <pb_type name="BUFGCTRL" blif_model=".subckt bufgctrl" num_pb="1"> |
| <input name="i" num_pins="2"/> |
| <input name="s" num_pins="2"/> |
| <input name="ce" num_pins="2"/> |
| <input name="ignore" num_pins="2"/> |
| <output name="o" num_pins="1"/> |
| </pb_type> |
| <interconnect> |
| <direct name="i" input="BUFG.I" output="BUFGCTRL.i"/> |
| <direct name="s" input="BUFG.S" output="BUFGCTRL.s"/> |
| <direct name="ce" input="BUFG.CE" output="BUFGCTRL.ce"/> |
| <direct name="ignore" input="BUFG.IGNORE" output="BUFGCTRL.ignore"/> |
| <direct name="o" input="BUFGCTRL.o" output="BUFG.O"/> |
| </interconnect> |
| </pb_type> |
| </complexblocklist> |
| </architecture> |
