vtr_flow/benchmarks/blif/6/bbara.blif

.model top
.inputs bbara_in_3_ bbara_in_2_ bbara_in_1_ bbara_in_0_ clock
.outputs bbara_out_1_ bbara_out_0_
.latch    n_n23 n_n60 re clock 2
.latch    n_n24 n_n61 re clock 2
.latch    n_n25 n_n62 re clock 2
.latch    n_n26 n_n63 re clock 2
.names bbara_in_2_ bbara_in_1_ bbara_in_0_ n_n61 n_n63 bbara_out_1_
1--01 1
-0-01 1
--001 1
.names bbara_in_3_ bbara_in_2_ bbara_in_1_ bbara_in_0_ n_n61 n_n63 \
bbara_out_0_
--0-11 1
---011 1
10--11 1
.names n_n60 [29] [28] [50] [168] n_n23
---1- 1
1-1-- 1
-1--1 1
.names bbara_in_3_ bbara_in_2_ [30] [42] [177] n_n24
---1- 1
----1 1
101-- 1
.names bbara_in_2_ [23] [37] [39] [179] n_n25
--1-- 1
0--1- 1
01--1 1
.names bbara_in_3_ bbara_in_2_ [34] [13] [15] n_n26
---1- 1
----1 1
101-- 1
.names bbara_in_3_ bbara_in_2_ n_n62 n_n63 [29]
-1-- 1
0-1- 1
1-00 1
.names bbara_in_3_ bbara_in_2_ bbara_in_1_ bbara_in_0_ n_n61 n_n62 [28]
--0--- 1
---0-- 1
-1---1 1
00--10 1
.names bbara_in_1_ bbara_in_0_ n_n60 n_n61 n_n63 [30]
--11- 1
---11 1
11-0- 1
.names bbara_in_1_ bbara_in_0_ n_n60 n_n61 n_n62 n_n63 [34]
---1-1 1
11101- 1
.names bbara_in_3_ n_n62 n_n63 [23]
100 1
.names bbara_in_2_ bbara_in_1_ bbara_in_0_ n_n60 n_n61 n_n62 [13]
111110 1
.names bbara_in_2_ bbara_in_1_ bbara_in_0_ n_n61 n_n63 [15]
-0--1 1
--0-1 1
1--01 1
.names bbara_in_1_ bbara_in_0_ n_n62 [37]
0-1 1
-01 1
.names bbara_in_3_ bbara_in_1_ bbara_in_0_ n_n60 n_n62 n_n63 [39]
0--01- 1
011--1 1
.names bbara_in_2_ bbara_in_1_ bbara_in_0_ n_n60 n_n61 n_n62 [42]
0--011 1
011-01 1
.names bbara_in_2_ bbara_in_1_ bbara_in_0_ n_n61 n_n63 [50]
11100 1
.names bbara_in_1_ bbara_in_0_ n_n60 n_n61 [168]
1101 1
.names bbara_in_2_ bbara_in_1_ bbara_in_0_ n_n60 n_n61 n_n62 [177]
-0--1- 1
--0-1- 1
111100 1
.names bbara_in_1_ bbara_in_0_ n_n60 n_n61 [179]
1101 1
.end