vtr_flow/benchmarks/blif/8/bbara.blif

.model top
.inputs bbara_in_3_ bbara_in_2_ bbara_in_1_ bbara_in_0_ clock
.outputs bbara_out_1_ bbara_out_0_
.latch    n_n23 n_n60 re clock 2
.latch    n_n24 n_n61 re clock 2
.latch    n_n25 n_n62 re clock 2
.latch    n_n26 n_n63 re clock 2
.names bbara_in_2_ bbara_in_1_ bbara_in_0_ n_n61 n_n63 bbara_out_1_
1--01 1
-0-01 1
--001 1
.names bbara_in_3_ bbara_in_2_ bbara_in_1_ bbara_in_0_ n_n61 n_n63 \
bbara_out_0_
--0-11 1
---011 1
10--11 1
.names bbara_in_3_ bbara_in_2_ bbara_in_1_ bbara_in_0_ n_n60 n_n61 n_n62 n_n63 \
n_n23
--0-1--- 1
---01--- 1
-1--1-1- 1
-11101-- 1
00--110- 1
-111-0-0 1
0-11011- 1
1-110100 1
.names bbara_in_3_ bbara_in_2_ bbara_in_1_ bbara_in_0_ n_n60 n_n61 n_n62 n_n63 \
n_n24
--0--1-- 1
---0-1-- 1
10--11-- 1
-0--011- 1
10---1-1 1
1011-0-- 1
-011-01- 1
-111100- 1
.names bbara_in_3_ bbara_in_2_ bbara_in_1_ bbara_in_0_ n_n60 n_n61 n_n62 n_n63 \
n_n25
--0---1- 1
---0--1- 1
00--0-1- 1
0011---1 1
10110100 1
.names bbara_in_3_ bbara_in_2_ bbara_in_1_ bbara_in_0_ n_n60 n_n61 n_n62 n_n63 \
n_n26
--0----1 1
---0---1 1
-1---0-1 1
10---1-1 1
-111110- 1
1011101- 1
.end