vtr_flow/benchmarks/microbenchmarks/false_path_mux.blif - third_party/vtr-verilog-to-routing - Git at Google

 .model top
 .inputs a b c sel
 .outputs out

 .names b b_inv
 0 1

 .names c b_inv sel d
 011 1
 100 1
 110 1
 111 1

 .names d a sel out
 011 1
 100 1
 110 1
 111 1

 .end
	.model top
	.inputs a b c sel
	.outputs out

	.names b b_inv
	0 1

	.names c b_inv sel d
	011 1
	100 1
	110 1
	111 1

	.names d a sel out
	011 1
	100 1
	110 1
	111 1

	.end