| #VPR Netlist statistics |
| num_primary_inputs;vpr.out;\s+\.input\s*:\s+(\d+) |
| num_primary_outputs;vpr.out;\s+\.output\s*:\s+(\d+) |
| num_pre_packed_nets;vpr.out;\s+Nets\s*:\s*(\d+) |
| num_pre_packed_blocks;vpr.out;\s+Blocks\s*:\s*(\d+) |
| num_netlist_clocks;vpr.out;\s+Netlist Clocks\s*:\s+(\d+) |
| |
| #VPR Packing Metrics |
| num_post_packed_nets;vpr.out;Netlist num_nets:\s*(\d+) |
| num_post_packed_blocks;vpr.out;Netlist num_blocks:\s*(\d+) |
| |
| #Device Metrics |
| device_width;vpr.out;FPGA sized to (\d+) x \d+ |
| device_height;vpr.out;FPGA sized to \d+ x (\d+) |
| device_grid_tiles;vpr.out;FPGA sized to \d+ x \d+: (\d+) grid tiles |
| device_limiting_resources;vpr.out;FPGA size limited by block type\(s\): (.*) |
| device_name;vpr.out;FPGA sized to \d+ x \d+: \d+ grid tiles \((\S+)\) |
| |
| #VPR Run-time Metrics |
| pack_time;vpr.out;^#*\s*Packing took (.*) seconds |
