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foss-fpga-tools
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third_party
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vtr-verilog-to-routing
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0a8dcf10219ceecb9d0b3e304cd0e987faea9c17
/
.
/
vtr_flow
/
sdc
/
samples
/
combinational_default.sdc
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create_clock
-
period
0
-
name virtual_io_clock
set_input_delay
-
clock virtual_io_clock
-
max
0
[
get_ports
{*}]
set_output_delay
-
clock virtual_io_clock
-
max
0
[
get_ports
{*}]
