| arch circuit vpr_revision vpr_status error num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_post_packed_blocks device_width device_height num_clb num_io num_outputs num_memories num_mult placed_wirelength_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration crit_path_routed_wirelength crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile crit_path_routing_area_total crit_path_routing_area_per_tile odin_synth_time abc_synth_time abc_cec_time abc_sec_time ace_time pack_time place_time min_chan_width_route_time crit_path_route_time vtr_flow_elapsed_time max_vpr_mem max_odin_mem max_abc_mem |
| k4_n4_v7_bidir.xml ch_intrinsics.v 30d086154 success 477 607 323 302 17 17 73 99 130 -1 -1 4323 7.15427 -644.01 -7.15427 13 2820 17 2655 18 9.92513 -904.128 -9.92513 0 0 6.75e+06 2.19e+06 -1 -1 -1 -1 0.03 0.01 -1 -1 -1 0.07 0.34 1.68 0.08 2.79 -1 -1 -1 |
