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foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
0cb3cbe4b64c5156c13cf39fdab9628c9dc2f4cd
/
.
/
libs
/
EXTERNAL
/
libsdcparse
/
test_sdcs
/
test5.sdc
blob: 10f237a171bb51825db64bb7bc53ee9fa9238988 [
file
]
create_clock
-
period
0
*
