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foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
0cb3cbe4b64c5156c13cf39fdab9628c9dc2f4cd
/
.
/
libs
/
EXTERNAL
/
libsdcparse
/
test_sdcs
/
test8.sdc
blob: 8cad4e8c9f3c737d0aa71063c8d97ab9fbf33e60 [
file
]
create_clock
-
period
1.0
*
_pll
