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foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
10967502edb0124a0d8f058fb42d1acde8a76d8b
/
.
/
abc
/
src
/
proof
/
ssc
/
module.make
blob: 55e845f8b26b789dfd89c48c992e3e0fb96e0d69 [
file
]
SRC
+=
src
/
proof
/
ssc
/
sscClass
.
c \
src
/
proof
/
ssc
/
sscCore
.
c \
src
/
proof
/
ssc
/
sscSat
.
c \
src
/
proof
/
ssc
/
sscSim
.
c \
src
/
proof
/
ssc
/
sscUtil
.
c
