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foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
1829a5e48a301876a7c7e40385dcae225dc3e8c6
/
.
/
test
/
basic
/
simplest.single_clock.blif
blob: 98cfffca05e5326a01d557dbbf700c75b8c73d7e [
file
]
.
model top
.
inputs a clk
.
outputs b
.
latch a l_a re clk
0
.
names l_a buf_l_a
1
1
.
latch buf_l_a b re clk
0
.
end
