Sign in
foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
25e5df9bac99258a495799fdfff7c8646946b93b
/
.
/
libs
/
EXTERNAL
/
libsdcparse
/
test_sdcs
/
test11.sdc
blob: c3f4baffad6f04b9a5cdebc76e4d4341636d0d98 [
file
] [
log
] [
blame
]
set_disable_timing
-
from
{
asdf
/
qwer
/
cin
}
-
to
{
awer
/
zxc
/
guy3w
}
set_disable_timing
-
from
asdf
/
qwer
/
cin
-
to awer
/
zxc
/
guy3w
set_disable_timing
-
from
[
get_pins
{
asdf
/
qwer
/
cin
}]
-
to awer
/
zxc
/
guy3w
