vtr_flow/benchmarks/blif/4/dk17.blif

.model top
.inputs dk17_in_1_ dk17_in_0_ clock
.outputs dk17_out_2_ dk17_out_1_ dk17_out_0_
.latch    n_n21 n_n48 re clock 2
.latch    n_n22 n_n49 re clock 2
.latch    n_n23 n_n50 re clock 2
.names dk17_in_0_ [23] [131] dk17_out_2_
--1 1
11- 1
.names dk17_in_0_ [27] [16] dk17_out_1_
--1 1
01- 1
.names dk17_in_0_ n_n48 n_n49 n_n50 dk17_out_0_
1-10 1
0-00 1
-100 1
.names n_n50 [22] n_n21
11 1
.names dk17_in_0_ n_n49 n_n50 [127] n_n22
---1 1
010- 1
.names dk17_in_1_ [24] [36] [37] n_n23
--1- 1
---1 1
11-- 1
.names dk17_in_1_ dk17_in_0_ n_n48 n_n49 [22]
1--- 1
-00- 1
--10 1
.names dk17_in_1_ n_n48 n_n49 n_n50 [23]
--1- 1
11-- 1
-1-0 1
.names dk17_in_0_ n_n48 n_n49 n_n50 [24]
-1-0 1
--00 1
100- 1
.names dk17_in_1_ n_n48 n_n49 n_n50 [27]
1-1- 1
1--1 1
-110 1
.names dk17_in_0_ n_n48 n_n49 n_n50 [16]
1000 1
.names dk17_in_0_ n_n48 n_n49 n_n50 [36]
1010 1
.names dk17_in_1_ dk17_in_0_ n_n48 n_n50 [37]
0111 1
.names dk17_in_1_ dk17_in_0_ n_n48 n_n50 [127]
010- 1
0-11 1
-100 1
.names dk17_in_1_ n_n48 n_n49 n_n50 [131]
0111 1
0010 1
.end