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foss-fpga-tools
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vtr-verilog-to-routing
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27949831b292ce45b71c470bcabc249f75f5d472
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.
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abc_with_bb_support
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default_out.resyn.blif
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# Benchmark "spram" written by ABC on Mon Mar 28 13:35:50 2011
.
model spram
.
inputs top
^
clock top
^
reset_n
.
outputs top
^
value_out
.
latch n7 top
^
FF_NODE
~
3
0
.
names top
^
reset_n top
^
FF_NODE
~
3
n7
01
1
.
names top
^
FF_NODE
~
3
top
^
value_out
1
1
.
end
