| <config> |
| <verilog_files> |
| <!-- Way of specifying multiple files in a project --> |
| <verilog_file>XXX</verilog_file> |
| </verilog_files> |
| <output> |
| <!-- These are the output flags for the project --> |
| <output_type>blif</output_type> |
| <output_path_and_name>ZZZ</output_path_and_name> |
| <target> |
| <!-- This is the target device the output is being built for --> |
| <arch_file>YYY</arch_file> |
| </target> |
| </output> |
| <optimizations> |
| <multiply size="MMM" fixed="1" fracture="0" padding="-1"/> |
| <memory split_memory_width="1" split_memory_depth="PPP"/> |
| <adder size="0" threshold_size="AAA"/> |
| </optimizations> |
| <debug_outputs> |
| <!-- Various debug options --> |
| <debug_output_path>.</debug_output_path> |
| <output_ast_graphs>1</output_ast_graphs> |
| <output_netlist_graphs>1</output_netlist_graphs> |
| </debug_outputs> |
| </config> |
