| ############################################## |
| # Configuration file for running experiments |
| ############################################## |
| |
| # Path to directory of circuits to use |
| circuits_dir=benchmarks/verilog |
| |
| # Path to directory of architectures to use |
| archs_dir=arch/timing |
| |
| # Add circuits to list to sweep |
| circuit_list_add=ch_intrinsics.v |
| |
| # Add architectures to list to sweep |
| arch_list_add=k6_frac_N10_mem32K_40nm.xml |
| |
| # Parse info and how to parse |
| parse_file=vpr_standard.txt |
| |
| # Pass requirements |
| pass_requirements_file=pass_requirements.txt |
