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foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
2df20a2e7c1d22850378ddf1f06e2e1267f6bcf9
/
.
/
utils
/
fasm
/
test
/
wire.eblif
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.
model top
.
inputs di0 di1 di2 di3 di4 di5
.
outputs do0 do1
.
names di0 di1 di2 di3 di4 di5 do0
000001
1
.
names di0 di1 di2 di3 di4 do1
00010
1
.
end
