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foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
3456100a525b68687fb81cf4f1b9e9c9b7e59882
/
.
/
vpr
/
test
/
wire.eblif
blob: 996f1f9b5a944af7f8f1a8f4c199dd2697c03eeb [
file
]
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model top
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inputs di
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outputs
do
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names di
do
1
1
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end
