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foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
51c5513da5925df425f6f6ff1fb5b2c74df21d4b
/
.
/
vtr_flow
/
sdc
/
samples
/
combinational_default.sdc
blob: a159ad1e227031781e32827232a6b2fe76a7bfde [
file
]
create_clock
-
period
0
-
name virtual_io_clock
set_input_delay
-
clock virtual_io_clock
-
max
0
[
get_ports
{*}]
set_output_delay
-
clock virtual_io_clock
-
max
0
[
get_ports
{*}]