Sign in
foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
637c3c953181efdb71652479d2a566ef7ff7f4e0
/
.
/
vtr_flow
/
benchmarks
/
microbenchmarks
/
and_latch.blif
blob: 469bce37ddfdeef91a0d2790dc99364d026b4c4a [
file
]
.
model top
.
inputs a b clk
.
outputs
out
.
names a b c
11
1
.
latch c
out
re clk
0
.
end
