Sign in
foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
65e7ee5bafe0b3f921ca4e5904bcb67eb7e12b3a
/
.
/
libs
/
EXTERNAL
/
libsdcparse
/
test_sdcs
/
test5.sdc
blob: 10f237a171bb51825db64bb7bc53ee9fa9238988 [
file
] [
log
] [
blame
]
create_clock
-
period
0
*