Sign in
foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
73a09f89b0a7f39e0dd680042fa6998e0f9b2b89
/
.
/
utils
/
fasm
/
test
/
wire.eblif
blob: 1f4c799752104043b1d96b14e9edb3ea618778a6 [
file
]
.
model top
.
inputs di0 di1 di2 di3 di4 di5
.
outputs do0 do1
.
names di0 di1 di2 di3 di4 di5 do0
000001
1
.
names di0 di1 di2 di3 di4 do1
00010
1
.
end
